CHAITHRA BK
Bengaluru
Summary
Results-driven Physical Design Engineer with over 8 years of expertise in the semiconductor industry, specializing in Place and Route (PNR), Timing Signoff, DRC Signoff, and IR/EM Signoff. Demonstrated success in delivering high-quality design solutions through the proficient use of tools including Fusion Compiler, ICC2, PrimeTime and Calibre. Hold an MTech degree in Engineering from R.V. College of Engineering, Bangalore. Possess strong scripting skills to automate and optimize design PPA. Actively pursuing opportunities to leverage technical proficiency to foster innovation in physical design engineering.
Overview
8
8
years of professional experience
1
1
Certification
Work History
Senior Staff Engineer
Samsung Semiconductor India
Bengaluru
04.2021 - Current
- Enhanced flow on advanced technologies including 4lpp, 4lpe, and others.
- Executed synthesis to signoff for high-performance CPU and GPU designs.
- Created floorplans with high utilization of area, power and performance goals.
- Resolved block level integration problems such as clock tree synthesis issues and top level clocking activities
- Performed static timing analysis on blocks using PrimeTime.
- Carried out Functional ECOs by analyzing schematic changes and performing necessary modifications in the existing layout.
- Specialized in Fusion compiler, Innovus, ICC2, ICV, Primetime, CLP, Genus and Calibre.
- Optimized synthesis results to meet timing constraints and power budgets.
- Demonstrated strong scripting skills to automate design processes and enhance efficiency
- Collaborated with other teams including CAD development, library characterization, circuit design, to achieve overall success of projects.
- Utilized scripting languages such as Tcl and Tk, Perl, Python to automate the flow and enhance efficiency
- Ensured compliance with relevant industry standards and regulations throughout the design process.
- Trained and guided new employees according to company standards and procedure
Physical Design Engineer
L&T Technology Services (LTTS)
12.2018 - 04.2021
- Skilled in PNR to signoff, specializing in single and multipower domain designs at block level.
- Developed powerplan ,preroute scripts for analog IP and collaborated with IP vendor to ensure quallity checks
- Developed custom clock preroutes for PLL outputs according to datasheet guidelines.
- Managed PNR and PV activity for hard clock IP's across approximately 100 configurations. and delivered GDS and netlist on schedule for all configuration, ensuring high quality
Design Engineer
Tessolve Semiconductor
06.2017 - 12.2018
- Collaborated with PNR engineer to enhance PNR recipe.
- Performed post-silicon validation, encompassing failure analysis, yield assessment, and functionality checks on various ICs.
- Performed complete project execution from testing to program implementation on ETS364 platform.
- Conducted power consumption measurements using power analyzers and oscilloscopes in order to measure energy efficiency of the system.
- Formulated comprehensive test plans and methodologies to validate wafer and packaged IC functionality.
Education
M.Tech - COMMUNICATION SYSTEMS
RV College of Engineering
01.2016
B.Tech/B.E. - electronics and communication engineering
T John Institute of Technology
Bangalore01.2014
Skills
- Physical Design
- PNR
- Synthesis
- Timing Closure
- Timing Analysis
- Signal Integrity
- Synopsys
- Cadence
- PV
- DRC
- LVS
- Caliber
- Primetime
- Clock Tree Synthesis
Certification
Physical Design, Chipedge Technologies Pvt Ltd
Projects
Acquisition and processing of stetho, ECG, blood pressure signals, 274 Days, Designed hardware for acquiring biomedical signals., Transferred the signals to web for easy accessibility., Processed the signals for desired feature extraction using MATLAB.
Languages
- English
- Kannada
- Hindi
- Tulu
Honors & Achievements
- Gold medalist in M.Tech issued by Visvesvaraya Technological University, Karnataka
- Multiple spot award and high performance award at work from Samsung for efficient and innovative work
- 2nd rank in Karnataka PGCET at State level entrance exam
Timeline
Senior Staff Engineer
Samsung Semiconductor India
04.2021 - Current
Physical Design Engineer
L&T Technology Services (LTTS)
12.2018 - 04.2021
Design Engineer
Tessolve Semiconductor
06.2017 - 12.2018
M.Tech - COMMUNICATION SYSTEMS
RV College of Engineering
B.Tech/B.E. - electronics and communication engineering
T John Institute of Technology
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