Mayur Kurkute

Organizations – GTM Application Engineering, Global Engagement Team.

Role – Synopsys physical design implementation tool benchmarking against competitive tools.

Experience –

Benchmarked the designs from the semiconductor companies on Synopsys PNR and sign-off tools, demonstrating superior quality of results.

• Google ARM CPU Benchmark.
• Converged the design of the latest ARM CPU core, achieving exceptional frequency targets.
• Realized a considerable power reduction without compromising the performance of the design.
• Deployed voltage optimization technologies and techniques.
• Incorporated sign-off tool correlations with PNR for improved implementation outcomes.
• Implemented custom global clock trees for the design, which cater to the high-frequency design requirements of better skew and latency.
• Apple GPU Block Benchmark.
• Completed design closure with aggressive area reduction goals.
• Power reduction solutions implemented with the latest tool technologies.
• Resolved the routing congestion in the design, leading to a high DRC count due to area reduction.
• Nordic Semiconductor Benchmarking.
• Achieved design closure and delivered exceptional results on an ultra-low-power design.
• Addressed various challenges, including numerous power supplies, domains, clocks, DVFS, and congestion issues within a complex floorplan.
• Enhanced power efficiency using the Design Space Optimization (DSO.ai) tool.
• Presented the latest updates on DSO.ai and prime power at the Nordic Semiconductor Tech Day in Trondheim, Norway.

All benchmarks are successfully won against the other tool vendors by showing the differentiation in the quality of the results, which were validated by the relevant sign-off flows of STA PrimeTime and PrimePower, ensuring proper correlation with the implementation tool.

Organizations – Graphic SOC Design Team.

Role – Physical Design and Design Planning for GPU SoC.

Experience –

• Compiled full-chip SoC RTL into a netlist and generated collateral for sub-hierarchies in abutted designs for synthesis.
• Executed floorplanning and placement of partitions, IPs, DFX, physical-only cells, and overlay cells with appropriate coverage, along with bump and RDL planning with the package team.
• Managed the placement of RTL ports for connections across hierarchies, timing budgeting, and implemented balanced global clock trunk routing with custom NDR pre-routes for critical signals.
• Conducted logical equivalence checks, and other miscellaneous verifications, to ensure design planning quality.
• Handled synthesis and place-and-route, achieving complete design closure for SoC interface fabric partitions.
• Developed automations to integrate bottom-up data into the full chip, ensuring data integrity for synthesis validation.

Organization – Intel Architecture Big Core Group.

Role – Physical Design and Sign-off Closure

Experience –

• Complete block-level closure for very high-frequency IA CPU cores.
• Contributed to numerous server and desktop CPU projects, achieving successful tape-outs.
• Synthesis and place-and-route, ensuring timing and DRC closure.
• Integration of hierarchical blocks and custom structural routing to meet high-frequency requirements.
• Custom clock tree balancing and routing to attain the best skew and latency for the designs.
• Block-level physical verification, extraction, timing analysis, and design convergence.
• CPU full chip-level extraction and timing analysis.
• Developed various automations.
• Rip-and-route utility for assessing what-if scenarios to improve timing and power.
• Advanced automated clock island routing at the full-chip level to enhance clock quality.
• Design and constraints generation, along with exchange flows for hierarchical designs.