Summary
Overview
Work History
Education
Skills
Accomplishments
Timeline
Generic

Anshu Sangal

R&D Staff Engineer
Noida

Summary

Working as a R&D Staff Engineer rich with 7+ years of industry experience in DFI controller(DFI5,DFI5.1, DFI5.2) and PHY VIP development & deployment for DDR3, DDR5, MRDIMM, HBM2/2E/3/4 & GDDR7.

Efficiently designed PHY VIP between DFI MC & Memory for HBM3/4, DDR5, MRDIMM. Skilled IP Verification engineer with strong analytical skills and comprehensive problem solving abilities, driven with customer centricity, adept in providing faster resolution to show-stopper issues.

Core competencies: IP verification, UVM, System Verilog, BFM development, Functional Coverage, Protocol checkers/scoreboard, Debugging skills and handson experience on Verdi GUI tool

Overview

7
7
years of professional experience
4032
4032
years of post-secondary education

Work History

Staff R&D Engineer

Synopsys Inc.
01.2024 - Current
  • DFI MC VIP design for DDR5 MRDIMM & successfully deployed with multiple customers.
  • Successfully delivered DFI PHY VIP design for DDR5 MRDIMM to the internal IP team for the efficient verification of MC IP.
  • Provided customised support of DFI VIP for HBM4 to multiple customers within strict deadlines.
  • Smartly planned & handled show-stopper customer cases & queries.
  • Helped multiple customers in their project integration with VIP by providing smart technical guidance.
  • Hiring new prospects to expand the VIP team & designed training modules for new hires.
  • Worked on multiple projects simultaneously and ensured timely releases by extensively using time management & planning skills.

Senior R&D Engineer

Synopsys Inc.
01.2021 - 12.2023
  • Customised support for DFI MC and DFI PHY VIP design for multiple customers.
  • Created Test Plans, Coverage Plans for the projects in hand.
  • Proposed detailed Design docs as per customer's requirement to avoid discrepancies between requirements & understanding.
  • Performed all possible Regressions by doing Regression setups with 100% functional coverage.

R&D Engineer 2

Synopsys Inc.
01.2018 - 12.2020
  • Efficiently delivered DFI DDR3 VIP along with test plans & testbench setup.
  • Provided support for DFI GDDR7 & DFI DDR5 VIP.
  • Added negative sequences to validate multiple checkers & scoreboard.
  • Added command wrapper sequences for LPDDR5.
  • Regression testing & cleaning to enhance the quality of VIP.

Education

ME - VLSI Design

Punjab Engineering College

BE - Electronics and Communication

Govt. College of Technology And Engineering

Skills

  • UVM structure flow
  • System Verilog
  • Verilog HDL
  • Shell scripting
  • Perforce commands
  • C
  • C
  • IPC
  • TCP/IP
  • Embedded system
  • MS-Office
  • Data Formatting

Accomplishments

  • Standing ovation Team award to deliver the DDR3 VIP in critical deadline for Broadcom.
  • Team Award for delivering DFI GDDR7, customised support for AMD.
  • Awarded for providing support for DFI MRDIMM & HBM.
  • GATE 2014 Qualified (97.9 percentile).
  • Winner in Robowar at Malviya National Institute of Technology, Jaipur.

Timeline

Staff R&D Engineer

Synopsys Inc.
01.2024 - Current

Senior R&D Engineer

Synopsys Inc.
01.2021 - 12.2023

R&D Engineer 2

Synopsys Inc.
01.2018 - 12.2020

ME - VLSI Design

Punjab Engineering College

BE - Electronics and Communication

Govt. College of Technology And Engineering

Similar Profiles

CREATE PROFILE
Anshu SangalR&D Staff Engineer