Dhatri Dave

Python, AI and Automation

• Owned end-to-end development from ideation to Proof of Concept for AI-driven Jira Automation Dashboard enabling natural-language-based ticket creation, bulk updates, and context aware access to latest comments using Jira Rest APIs.
• Built a large-scale log analysis framework that reduced multi-GB simulation logs to structured CSV(10x size reduction), making them usable for AI based debugging and significantly reducing LLM based token consumption.
• Integrated log analytics and pre-processing pipelines into CI/CD flows to improve Automation readiness of verification environments.
• Implemented a waveform-to-CSV conversion utility using Cadence Verisium Debug Python APIs, enabling automatic checker generation and data-driven debug.
• Designed AI-assisted workflows to produce compile-clean testbench generation, refactoring, and automated assertion generation
• Developed a Streamlit-based web GUI to expose AI-powered tools for Design Verification flows

Cadence Tools, Verification Methodology & Vendor Engagement

• First PoC for Cadence tools flows for multiple teams with total of 100+ engineers
• Standardized setup and enablement flows for Verisium Debug, Codeminer, Waveminor.
• Applied simulation and debug option tuning to improve runtime performance, waveform size, and overall regression efficiency achieving 50% reduction in runtime and size.
• Evaluated ML assisted debug tools in collaboration with EDA vendors providing structured feedbacks for usability and performance improvements.
• Identified, documented and tracked tool issues and enhancement requests through regular sync-ups with Vendor R&D teams, influencing tool roadmap and feature improvements.

Verification Infrastructure, Flow Enhancements & CI/CD

• Consolidated 50+ makefiles into unified, scalable Makefile architecture, deployed across 4 teams(100+ engineers)
• Unified local compile wrappers and simulation wrappers into standardized single wrappers.
• Developed shell and python based Automation to generate Git command sequence to reproduce a repo.
• Contributed to creating failure details for re-running fails automatically and integrated into CI/CD involving bamboo pipelines.
• Evaluated and onboarded internal AI tools based on DV usecase feasibility evaluation.

• Enhanced regression environments for SOC subsystem by upgrading and extending existing Python and shell based solution
• Developed Automation for regression execution, log parsing, status tracking and debug launch (verdi)
• Worked extensively on toggle coverage analysis using Cadence IMC, automated coverage from CSV to cover holes for coverage closure.
• Created python scripts to generate C testcase with embedded assembly from hexadecimal instruction sequences.
• Contributed to python based testcase generation (page table, interrupts) for subsystem verification.
• Worked on compile clean testbench for different builds in a UVM-based SoC testbench environments.

(Intern, Jan 2019- June 2019; converted to full-time role)

• Member of L3 Cache testbench teams for Dynamic Shared IQ, working at Unit Level on Cortex-A class (v8+) architectures.
• Developed and maintained assembly testcases, worked with ELFs, disassembly, and Makefile based flows.
• Built python utilities for signal list comparison and connectivity checks, generating CSV reports for mid-match analysis.
• Managed long-running regressions using LSF, including project codes and user ID handling.
• Debugging and fixed UVM testbench issues across regression cycles.
• Worked with test plans and Dimensions RM, automating testcase and coverage result updates directly to tool for Sign off using perl, python and html.
• Converted and analysed waveforms(FSDB, VCD, WLF) and generated coverage reports via CLI tools.

• Conducted labs for Software Engineering and Computer Architecture
• Guided student teams through project ideation, design documentation and implementation.
• Designed and conducted labs for Assembly Language Programming and Computer Organization and Architecture