Debraj Ganguly
Bangalore
Summary
Accomplished RTL Design Engineer with five years of experience in ASIC and FPGA design, specializing in RTL coding, logic synthesis, and verification. Demonstrates proficiency in Verilog and SystemVerilog, coupled with expertise in high-performance digital circuit design, timing analysis, and low-power techniques. Adept at utilizing EDA tools such as Cadence, Synopsys, and Siemens EDA while collaborating across teams to deliver optimized IP solutions. Strong analytical capabilities drive a commitment to team success, and exceptional results in demanding environments.
Overview
5
5
years of professional experience
Work History
ASIC Design Engineer, Staff
Synopsys India Pvt. Ltd.
Bangalore
2023.02 - Current
- Own microarchitecture and RTL specification of UniPro protocol IP for both commercial and functional safety, automotive applications.
- Developed RTL for upcoming version of UFS/UniPro protocol specification with improving performance by 15%
- Supported over 50 customer issues at various stages of design cycle, including silicon bring-up, ECO, and contributed to 20+ timely releases to customers.
- Developed functional safety features for UFS protocol IP, and contributed to FuSa analysis like FMEDA and DFMEA.
- Achieved customer's silicon success for over 6+ projects incorporating UFS/UniPro protocol IP.
Senior Engineer
Samsung Semiconductor India Research
Bangalore
2021.11 - 2023.02
- Developed micro-architecture and RTL specification for wide range of Encryption and Hash IPs like AES, SHA, GCM, HMAC etc.
- Improved the throughput of a Hash IP by 1.5 Gbps (~20%) and contributed to the signoff of a critical project
- Developed scripts for faster RTL development and produce results for different configuration of the RTL which improves the production time by 40%
- Developed RTL of a lightweight block cipher from the scratch which has better performance than AES.
Member of Technical Staff
Siemens EDA (Mentor Graphics) India Pvt. Ltd.
Noida
2020.08 - 2021.11
- Designed and developed of CDC and RDC analysis tool (Questa CDC, RDC)
- Contributed to 5 timely releases to customers and 30+ customer cases, including on-call support to customers, and helped them sign off on CDC/RDC issues for large SOC design.
- Developed a feature that will assist the customer by predicting the potential misses of constraints in the design.
Education
Bachelor of Technology - Electronics and Tele-communication Engineering
Indian Institute of Engineering Science & Technolo
Shibpur, West Bengal, India2020-07
Skills
- RTL Design and Coding (Verilog, SystemVerilog)
- Developing micro-architecture and functional specification with PPA optimization
- Low Power and UPF design techniques
- Synthesis, timing closure, LEC and DFT
- RTL quality checks for Lint, CDC and RDC
- RTL design for functional safety in automotive application
- Bus Protocols: AMBA(AXI, AHB and APB)
- Formal verification with SVA
- Scripting(Python, Tcl)
- Software languages(C,C)
- EDA tools: Xcelium(Cadence), VCS(Synopsys), Spyglass, VcSpyglass(Synopsys), Questa(Siemens EDA), Design Compiler, Fusion Compiler, Formality, PrimeTime, PrimePower(Synopsys), TestMax(Synopsys), Verdi(Synopsys)
Languages
Bengali
First Language
English
Proficient (C2)
C2
Hindi
Advanced (C1)
C1
Timeline
ASIC Design Engineer, Staff
Synopsys India Pvt. Ltd.
2023.02 - Current
Senior Engineer
Samsung Semiconductor India Research
2021.11 - 2023.02
Member of Technical Staff
Siemens EDA (Mentor Graphics) India Pvt. Ltd.
2020.08 - 2021.11
Bachelor of Technology - Electronics and Tele-communication Engineering
Indian Institute of Engineering Science & Technolo