Manoj Kumar Rishi
Bengaluru
Summary
Detail-oriented, organized and meticulous employee. Works at fast pace to meet tight deadlines. Enthusiastic team player ready to contribute to company success.
Overview
11
11
years of professional experience
Work History
Staff Engineer, ASIC Design
Synopsys India Pvt. Ltd.
10.2018 - Current
- Leading IP Verification Team in multi-protocol supported Combo PHY IP's for UVM TestBench development, debugging customer issues and managing multiple concurrent projects and ensuring timely completion for Customer releases.
- Experience in verification of PCIE, USB, Ethernet and HDMI rates supporting combo PHY IP.
- Collaborated with cross-functional teams to Customer issues in RTL and Gate level verification and optimizing overall performance.
- Expertise in managing independent test-benches using Verilog and UVM to support verification of IP's available to customer releases.
- Team lead and asset for low power verification of Combo PHY IP and responsible to solve customer issues.
- Lead to perform regressed verification on IP's supporting HDMI PHY and PCS Layers.
Senior ASIC Verification Engineer
PerfectVIPs Techno Solutions Pvt. Ltd.
10.2015 - 09.2018
- Worked as the senior team member in IP Verification team of Synopsys India Pvt. Ltd. as the Contractor during period Dec''2016 to Sept'2018.
- Worked on SOC Verification projects supporting verification of blocks Serial Attached SCSI (SAS), and AMBA AHB during period Oct'2015 to Dec'2016.
ASIC Verification Engineer
SiWaves Technologies Pvt. Ltd.
03.2014 - 06.2015
- Worked as a Verification team member in a project to verify CAN 2.0 protocol IP. Involved in Sequence and Interface development tasks using UVM.
- Worked on verification of IP's including AMBA AHB and AXI. Developed transactions and sequences in UVM testbench as per specifications.
- Grown skills in testbench development activities and RTL simulation debugs.
ASIC Design Verification Engineer Trainee
Maven Silicon VLSI Training Center
09.2013 - 03.2014
- Development knowledge in IP Design and Verification. Performed activities to develop test-benches from scratch using Verilog, System Verilog and UVM.
- Projects done during training - Router 1x3, Dual Port RAM, SPI and UART.
Education
Bachelor of Technology - Electronics And Communication Engineering
Punjab Technical University
Jalandhar07.2013
High School - Physics, Chemistry And Mathematics
Punjab School Education Board
Mohali, India03.2009
Skills
- RTL Design knowledge using Verilog and System Verilog
- IP Verification using Verilog, System Verilog and UVM
- Low Power Verification using UPF
- SoC Verification knowledge
- Verification of RTL, Gtech and Gate level simulations
- Tools: VCS, Verdi and NCSim
- Scripting: Perl, Python and Makefile
- Issue management tools: JIRA and Mantis
- Version management tools: Perforce
- Operating Systems: Linux and windows
- Root Cause Analysis
- Design development
- Engineering Documentation
- Interpersonal Communication
Languages
English
Hindi
German
Punjabi
Timeline
Staff Engineer, ASIC Design
Synopsys India Pvt. Ltd.
10.2018 - Current
Senior ASIC Verification Engineer
PerfectVIPs Techno Solutions Pvt. Ltd.
10.2015 - 09.2018
ASIC Verification Engineer
SiWaves Technologies Pvt. Ltd.
03.2014 - 06.2015
ASIC Design Verification Engineer Trainee
Maven Silicon VLSI Training Center
09.2013 - 03.2014
Bachelor of Technology - Electronics And Communication Engineering
Punjab Technical University
High School - Physics, Chemistry And Mathematics
Punjab School Education Board
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