JAI RAM MEENA

• Supporting key customer (Microsoft) for various critical issue & latest tool enhancement deployment into pnr flow related to fusion compiler
• Driving weekly Tech meeting with Customer to provide update on issues & new feature/tool enhancement.
• Managing & leading India AE team responsible for supporting the Microsoft account.
• Worked closely with customer on TSMC 2nm & 3nm tech node to resolve flow issues & tool related bugs.
• Supported & resolved various critical issues like PNR full flow runtime, FC-PT correlation, congestion/shorts, antenna miscorrelation (fc vs calibre), timing convergence, MAX tran/cap recipe etc.
• Worked on critical block for full flow (syn & pnr) total runtime reduction from 14 days to 8.5 days & delivered recipe to customer.
• Compiling & sending weekly team work status report to management.
• Using internal AI tools to create utility for debug & automate the tasks
• Running latest feature enhancement test regression(SQS, EIM, ERI, EZI, Early GR, TEP etc.) & providing feedback to RnD.
• Visiting customer site to provide onsite support & build strong relationship with customer.

1. Server Soc, Intel3
Responsibilities: January 2024 – June-2025

• Implemented critical multi voltage block with 250k instance count, 59 macros, 294 TSV, achieving 2.8GHz frequency.
• Synthesis, scan insertion, and complete PnR implementation and signoff were performed.
• Floor planning of Hard Macros, voltage area & SPG with TSV placement guidelines are major task.
• Timing convergence & latency targets are critical, for timing closure & latency targets multiple experiments were done (Data path controlling, Level shifter placement planning, RTL/architecture changes, skew groups, temp clocks, H tree)..

Responsibilities: March 2023 – December 2023

• Executed block implementation of 1 critical block of 1M instance count & 2.8 Ghz frequency.
• Tasks included Synthesis -> Scan insertion -> Complete PnR Implementation.
• Floor planning of Hard Macros, voltage area & SPG with TSV placement guidelines are major tasks.
• IR/RV & PDN checker review Ownership of 4 blocks.

2. Network, Tsmc 5nm: April 2022 – Jan 2023
Responsibilities:

• Handled implementation of 1.1 & 1.2 M instance count block.
• Tasks included Synthesis -> Scan insertion -> Complete PnR Implementation.
• Floor planning of 100 Hard macros in 1 partition.

3. Discrete Graphics, Tsmc 7nm: July 2021 – March 2022
Responsibilities:

• Handled 0.8M instance count block.
• Pipeline placement of register & implemented multi source clock tree synthesis.
• Worked on RV analysis along with partition implementation.

4. Discrete Graphics, Tsmc 7nm: Oct 2020 – June 2021
Responsibilities:

• Handled 2 critical partition of 1.7M & 2.4GHz, 1.2M & 2.4Ghz.
• Tasks included Synthesis -> Scan insertion -> Complete PnR Implementation, ECO implementation & sign-off.
• RPD placement based on the data flow for timing closure.
• High run time & utilization were major challenges to close design on time.

5. Discrete Graphics, Tsmc 7nm: June 2020 – oct 2020
Responsibilities:

• Handled 1.7M instance & 2.4GHz freq. block implementation.
• Tasks included Synthesis -> Scan insertion -> Complete PnR Implementation, ECO implementation & sign-off (timing, caliber & PDN)
• Floor planning of RPD’s for timing closure based on data flow.
• Routing & high utilization of partition were major challenges of the design.

6. Discrete Graphics, Tsmc 7nm: April 2020 – MAY 2020
Responsibilities:

• Handled implementation of 2 routing critical partitions in ECO phase
• Task included timing, caliber, RV closure.
• Assisted RCGs during implementation in Eco implementation.

7. PCH Design, Intel 14nm (A0& B0): August 2018 – March 2020
Responsibilities:

• Handled implementation of 2 very complex multi voltage blocks of 1.7M & 0.7M instance count.
• Tasks included Synthesis -> Scan insertion -> Complete PnR Implementation, ECO implementation & sign-off (timing, caliber & PDN).
• Successfully resolved 10K shorts with various floorplan experiments.
• Timing & RV closure were the main challenges in the design.
• Provided timing, caliber & RV Eco tcls for various partition during Eco Phase.