Karishma Jamwal

1. Successfully doing integration testing for RTL to GDS process for DigitalOnTop. Also contributing in testing Design systems(DP/TP, Standard cell libraries and memories) for whole RTL to GDS process.
2. Working with hierarchal and few real time
design/IPs for testing
3. Developed scripts and automated processes to streamline whole testing.
4. Used various CAD (cadence/synopsys ) tools for synthesis, placement, routing, static timing analysis and DFT .
5. Identified and solved design issues to eliminate design errors.
6. Mentored junior engineers by providing guidance on best practices and industry standards, fostering professional growth.

1. Creation and modification of the package drawings, such as footprint drawings, scalable package outlines, and packing and marking files for marketing purposes.

2. Streamlined design processes, resulting in increased efficiency and faster project completion times.

1. Creation of PCB components in the Altium tool, and then converting the schematics and footprints in other EDA tools.

2. Responsible for qualifying PCB components design from an external vendor.

• Creation of PCB components in the Altium tool, and then converting the schematics and footprints in other EDA tools.