Adarsh Tomar

Ownership

• Owned Geometry cluster in fixed function pipeline, validating 5+ units while actively maintaining and enhancing the verification environment, and identifying the holes for upcoming projects.
• Mentored interns and college graduates to ramp up on verification and test environments.
• Experienced in end-to-end validation of design features, which involves corner case scenario checking to make the RTL design more robust.

UVM

• Worked on enhancing UVM sequences, transactions, and agents to meet DUT injection requirements; demonstrated a working knowledge of UVM methodology.
• Experienced in modifying unit-level scoreboards to verify RTL behavior against expected outputs, ensuring functional correctness.

System Verilog

• Debugged and fixed SystemVerilog testbench issues by updating checkers and trackers for better failure visibility and analysis.
• Root-caused testbench and RTL failures, coordinating with design and modeling teams to ensure timely resolution of critical bugs.
• Created and integrated SystemVerilog assertions and coverage for new features across unit-level and cluster-level test benches.
• Designed stall modules for unit-level interfaces to delay credit signals from bottom to top units for timing and stress testing.
• Generated constrained-random test cases in SystemVerilog to maximize functional coverage, and stress critical design paths.

Scripting

• Proficient in Perl scripting for developing automated checkers and improving verification efficiency.

• Executed targeted simulations and large-scale regressions to validate complex IP and cluster-level designs
• Owned triaging responsibilities for a sub-cluster across three different verification projects
• Collaborated with designers across multiple clusters to resolve inter-cluster dependencies and code integration issues
• Developed white-box functional coverage using SystemVerilog (covergroups, coverpoints, bins) and achieved coverage closure across multiple features