ADARSHAM .

1. Formal Verification on I/O Muxes Design Types

Roles and Responsibility

• Debugging and Witting of System Verilog Assertions .
• Tested functionality, performance and compliance of each product against design specifications to maintain strong development standards and high customer satisfaction.
• Created and maintained database of common and known testing defects.

Tools

• Cadence Jasper

2. Gate Level Simulation on Live Project

Roles and Responsibility

• Generated automated group file by writing python scripts that reduced the efforts and time taken significantly.
• Created and maintained database of common and known testing defects.
• Compiled weekly reports for Passing/Failing Testcases for Best Cases and Worst Cases Scenario.
• Tracked project schedules and encouraged teams to complete tasks on time.

Tools

• Cadence VManager

3. SoC Level Verification of an IP on Live Project

Roles and Responsibility

• Debugging register Testcases of IP .
• Generating waveform and study the characteristics of IPS protocol .
• Generating Register Testcases from the XMLs .

Tools

• Cadence Xcelium