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Avee Kumar
Silicon Validation Engineer
Delhi
Summary
Intelligent and qualified Silicon Validation Engineer with 2 years of experience in debugging issues during Pre-Si and Post-Si Validation and Si Bring-up. Talented at documenting and reporting for accurate recordkeeping. Enthusiastic professional with focus on effectively analyzing test results.
Overview
2
2
years of professional experience
6
6
years of post-secondary education
Work History
Silicon Validation Engineer
Qualcomm
Bangalore
06.2020 - Current
- Experienced in Pre-Si Validation on FPGA based hardware platform.
- Participated in Post-Si Validation with actual Si on hardware board based platform with objective of driving product to mass production.
- Performed detail Si Validation analysis for the process Bring-up.
- Execution and Automation of test cases to increase test coverage under different external conditions.
- Worked with SoC development team and Platform team for troubleshooting of hardware and software issues.
- Compiled Si Validation reports and communicated Si analysis result to multiple design and process development engineering teams.
Intern
Cadence System Design
Bangalore
05.2019 - 07.2019
- Documented Critical Design Review and Final Design Review for low power, low area D flip flop and Power-On Circuit (POC) cell at Samsung 7nm node using Virtuoso ADE Assembler and Maestro view.
- Wrote test benches for setup, hold, C2Q delay and leakage for D flip flop and power, delay and hysteresis for POC cell on
various PVT corners and Monte Carlo simulation on worst case corners. - Calculated jitters using Eye-diagram caused by ISI and supply noise with Pseudo Random Binary Sequence.
- Performed Quality Checks-PERC, Asserts Checks and Floating Gate/Bulk Checks and Reliability simulation(HCI and BTI).
Education
M.Tech - VLSI Design Tools & Technology
Indian Institute of Technology
Delhi 05.2018 - 06.2020
B.Tech - Electronics And Communication Engineering
Delhi Technological University
Delhi 05.2013 - 06.2017
Skills
Si bring-up and Debugging
Lauterbach Trace32
Scripting skill in the context of Trace and debug
Good understanding of ARM architecture
Proficient in C and Verilog
Good team-work spirits
Quick learner
Accomplishments
- Secured 99.84 percentile in Graduate Aptitude Test in Engineering (GATE) 2018 and 99.7 percentile in GATE 2017 in ECE.
- Stood among top three trainees in the post training evaluation test conducted by ITTM at MTNL, Delhi.
- School Topper in XII with 96.67% in PCM.
Interests
Timeline
Silicon Validation Engineer
Qualcomm
06.2020 - Current
Intern
Cadence System Design
05.2019 - 07.2019
M.Tech - VLSI Design Tools & Technology
Indian Institute of Technology
05.2018 - 06.2020
B.Tech - Electronics And Communication Engineering
Delhi Technological University
05.2013 - 06.2017