Summary
Overview
Work History
Education
Skills
Long distance Running , Trekking , Cycling
Timeline
Generic

AvinasH M

Pre Silicon Validation Engineer
Bengaluru

Summary

Accomplished Pre Silicon Validation Engineer with a proven track record at Intel Technologies, showcasing expertise in ASIC and DFD verification, and System Verilog. Excelled in leading full verification cycles, enhancing security validation, and mentoring junior engineers, demonstrating exceptional leadership and technical skills.

Overview

10
10
years of professional experience
2
2
years of post-secondary education

Work History

Pre Silicon Validation Engineer

Intel Technologies
01.2019 - Current

Worked on SOC verification - Early debug IP's .

Roles and Responsibilities

  • Write test cases to verify end points that security IP can access .
  • Security authentication verification with firmware download.
  • Involved in VAL bring up of compute die in one SOC . Handled multiple resets until traffic is driven from various sources
  • IP verification - VAL Lead
  • IP level Verification of trace packet into memory.
  • Complete ownership of one debug IP with verification support to other debug IPs
  • Executed more than one full verification cycle from test plan to release
  • Worked on early bug finding techniques with formal verification tools - Jasper Gold
  • Familiar with sub system verification with integration of debug IPs into sandbox model
  • Security validation of registers with Intel SAI
  • Mentored junior engineers in best practices for validation engineering methodologies improving team skillsets.

Senior ASIC Design Verification Engineer

SASIC Technologies Private Limited
Bengaluru
04.2016 - 12.2018
  • Worked for different clients with expertise in IP verification.

Client -1

  • Exclusively worked in bridge protocols , network layer to APB and OCP bridges.
  • Responsible for scoreboard bringup and development , functional coverage closure.
  • Responsible for reorder buffer agent development .
  • Worked closely with design teams for 100% code coverage.

Client -2

  • Worked to create test plan for Analog to digital converter
  • Responsible for test bench development and environment bringup.
  • Responsible for assertion extraction and development.
  • Involved in checker development and functional coverage and regression closure

Client -3

  • Verified MIPI I3C design with the MIPI I3C verification IP provided by Synopsys.
  • Introduced error injection techniques to the design inorder for the DUT to detect the error and fail safely .
  • Verified the MIPI I3C protocol checks using assertions.
  • Worked on a comprehensive register testing for the same.
  • Closed on functional coverage , regressions and testplan reviews.

Asic Design Verification Engineer

CVC Private Limited
07.2014 - 03.2016

My responsibilities include :

  • To create formal verification assertion test cases for two assertion IP's APB and AHB specifications using VC formal.
  • Ran entire regression test suite of VIP for above specifications
  • Followed strict process of source code management by using source code management tools

Education

Mtech - in Microelectronics And Control Systems

PES Institute of Technology
Bengaluru
08.2013 - 06.2015

Btech - Electronics And Communications Engineering

BNM Institute of Technology
Bengaluru, India
04.2001 -

Skills

ASIC verification

Long distance Running , Trekking , Cycling

Participated in various long distance running events and completed more than 3 full marathons and one ultra marathon . Trekked in the western ghats and himalayas various times

Timeline

Pre Silicon Validation Engineer

Intel Technologies
01.2019 - Current

Senior ASIC Design Verification Engineer

SASIC Technologies Private Limited
04.2016 - 12.2018

Asic Design Verification Engineer

CVC Private Limited
07.2014 - 03.2016

Mtech - in Microelectronics And Control Systems

PES Institute of Technology
08.2013 - 06.2015

Btech - Electronics And Communications Engineering

BNM Institute of Technology
04.2001 -
AvinasH MPre Silicon Validation Engineer