Summary
Overview
Work History
Education
Skills
References
Timeline
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BHARATH KUMAR NAYAKA B R

BHARATH KUMAR NAYAKA B R

Bangalore

Summary

Verification lead with 14 years of experience in IP, subsystem, and SoC-level verification, with a strong specialization in system-level validation and firmware-hardware co-validation using the Zebu emulator. Currently leading efforts on Intel server SoCs, focusing on power management, manageability, crash log, and RAS flows—ensuring end-to-end validation from architectural intent to functional implementation.

Actively involved in architecture definition and feature scoping, collaborating with architects, and firmware teams to shape and validate complex power and reliability features. Recognized for expertise in firmware debugging, hardware debugging, system architecture, and modern verification methodologies, with a proven track record of delivering results in high-performance design environments.

Overview

14
14
years of professional experience

Work History

Pre Si/ Validation Engineer

Intel Corporations
Bangalore
05.2018 - Current
  • Executed validation of Server Power Management flows on emulation platform.
  • Integrated PM IPs and generated firmware images for virtual environment compatibility.
  • Developed comprehensive test sequences for core performance and thermals.
  • Enabled checkers to validate functionality across all IPs in SOC.
  • Conducted debugging sessions across IPs to resolve technical issues.
  • Performed regression testing to ensure stability and performance metrics.
  • Collaborated with a team of five in implementing power management standards effectively.

Senior Engineer

Qualcomm INC
Bangalore
06.2017 - 04.2018
  • Verification lead for the PA Simulations.
  • Understanding of Architecture changes, Test plan, Testcase development, regression and coverage closure.
  • Project name: Power Aware Simulations on Camera Subsystem.
  • Type: Sub system level Verification
  • Team size: 1
  • Tools: DVE, Verdi
  • Description: Worked on Power Aware Simulations on RTL.

Pre Si/Validation Engineer

Intel Corporations
Bangalore
03.2016 - 06.2017
  • Verification lead for the security.
  • Understanding SOC architecture, Security flows, access control flows. Verification Plan, Environment Integration, Testcase development, regression coverage.
  • Project name: Crypto Subsystem and SoC Security
  • Type: SoC level Verification
  • Team size: 3
  • Tools: DVE, Verdi
  • Description: Security is the critical feature in any SoC. Worked on secure boot flow, secure access control for complete SoC.

Senior Software Engineer

Samsung R & D Institute India
Bangalore
04.2013 - 03.2016
  • Developed verification environment utilizing SV and UVM methodologies.
  • Wrote test cases and implemented coverage for effective regression management.
  • Executed GPU verification project focusing on Color Raster Operations at IP level.
  • Ensured compliance with Graphics Pipeline standards and credit-based interfaces.
  • Utilized VCS, Verdi, and DVE tools to enhance verification processes.
  • Gained in-depth understanding of GPU architecture and CROP functionality.

R & D Engineer I

Mirafra Technologies
Bengaluru
10.2011 - 03.2013
  • Development of System Verilog Assertions test cases while validating synthesis on Zebu.
  • Implemented scripts for effective regression file management.
  • Executed validation of SVA support in Zebu emulation tool.
  • Contributed to a five-person team focused on project success.
  • Employed VCS, Modelsim, and Simvision for enhanced testing processes.

Education

B Tech - ECE

NIT
Warangal
01-2011

Skills

  • Verilog, SystemVerilog, UVM
  • C, C, Python
  • VCS, Verdi, DVE, Zebu
  • Server power management: power states, Idle states, DVFS, thermals
  • Server Manageability: Firmware flows, telemetry, RAS, crashlog, system recovery
  • SoC security: secure boot, access control
  • Tensilica (Xtensa) uController for PM
  • UPF-based power-aware verification
  • GPU architecture, graphics pipeline
  • PCIe subsystem integration
  • H264 video compression
  • DDR memory, controller interfaces
  • OCP, AXI, AHB, APB protocols
  • Q/P channel power interface validation

References

References available upon request.

Timeline

Pre Si/ Validation Engineer

Intel Corporations
05.2018 - Current

Senior Engineer

Qualcomm INC
06.2017 - 04.2018

Pre Si/Validation Engineer

Intel Corporations
03.2016 - 06.2017

Senior Software Engineer

Samsung R & D Institute India
04.2013 - 03.2016

R & D Engineer I

Mirafra Technologies
10.2011 - 03.2013

B Tech - ECE

NIT

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BHARATH KUMAR NAYAKA B R