Summary
Education
Skills
Personal Information
Professional Training
Academic Projects
Verilog Projects
Languages
Extracurricular Activities
Hobbies and Interests
Disclaimer
Timeline
Generic

Bhashyam Lakshmi Venkatesh

4-187,75 Tyalluru,Pedakurapadu(MD),Palnadu(DT)

Summary

To Pursue my career in an organization with performance-oriented environment for achievement of personal advancement. Being ambitious and hardworking, I am looking forward to challenging my potential and be worthy of Management trust and confidence.

Education

B.TECH(ECE) -

Baptala Engineering College
04.2023

Intermediate -

Narayana Junior College
01.2019

SSC -

SVVN High School
01.2017

Skills

  • Windows
  • Linux
  • Good at Digital electronics and VLSI Design
  • Basic knowledge on protocols
  • Verilog
  • System Verilog
  • UVM
  • C-Language
  • Python
  • TCSH
  • TCL

Personal Information

  • Father's Name: Bhashyam Brahmaiah
  • Date of Birth: 12/26/2001
  • Gender: Male
  • Nationality: Indian
  • Marital Status: Unmarried

Professional Training

Design Verification Trainee, Sumedha IT, Hyderabad, 07/2023, Present

Academic Projects

Minor project done on smart charging station for electric vehicle(IOT). 

Major project done on Design of DGS incorporated MIMO antenna at sub6-GHZ for 5G applications(B.TECH).

Verilog Projects

  • SPRAM: Single port Random Access Memory(SPRAM) is a memory which we can do either write operation or read operation at one time.If write signal is high write operation will takes place Else write signal is low Read operation will takes place.
  • DPRAM: Dual port Random Access Memory (DPRAM) is a type of memory in which we can read & write simultaneously.In this project it consists of read enable and write enable input Ports. If Write enable is high we can write data into memory and if read enable is high, we can read from the memory at specified address.
  • FIFO: FIFO (First-In-First-Out) is used for buffering data between asynchronous processes or synchronous process. It stores data items in a sequential manner, allowing the oldest data to be read first. Proficient in designing and implementing FIFO modules using Verilog for efficient data management and synchronization in digital systems
  • APB PROTOCOL: The Advanced Peripheral Bus (APB) protocol is a low-speed interface used to connect lowbandwidth peripherals to a system-on-chip (SoC). It employs a simple, single-master, multiple-slave architecture, facilitating efficient communication with peripherals in digital systems.

Languages

Telugu
English

Extracurricular Activities

Participated in TECHKSHETRA(National level fest) organised by college in 2K19. 

Participated in BECTAGON 2K23(National level technical fest) organised by college. 

Possessive of a calm, relaxed approach to situations, people, events.

Hobbies and Interests

  • Playing Badminton
  • Listening to Music
  • Gardening
  • Playing Cricket

Disclaimer

I hereby declare that the above details are correct to the best of my knowledge.

Timeline

B.TECH(ECE) -

Baptala Engineering College

Intermediate -

Narayana Junior College

SSC -

SVVN High School
Bhashyam Lakshmi Venkatesh