Chaitanya C

Results-driven Physical Design Engineer with over 6 years of experience in executing the entire PNR flow and managing all signoff activities. Proficient in utilizing advanced design tools and methodologies to optimize chip layouts, ensuring adherence to quality standards and project deadlines. Strong analytical skills enable effective problem-solving, contributing to successful project completion and client satisfaction.

Industry Oriented Trainee in VLSI PHYSICAL DESIGN, Institute of Silicon Systems Pvt Ltd., Hyderabad, Telangana from December 2017 to June 2018

Client : Qualcomm India pvt ltd 

Block name : hm_mm_tile Technology : Tsmc 4nm 

Worked on block level RTL to GDSII implementation which includes floor-planning, power planning, Placement, CTS, Feed through buffering,Route. Worked on signoff flows extraction, timing caliber violations, LEC and CLP violations.

We faced challenges for convergence of block as hm_mm_tile is having around 3500 feedthroughs and for critical feedthroughs we need to take care and manual feedthrough buffering is done for them.

We faced congestion issues near the L cut shape of the block as the functional cells and feed through buffers are placed at same region. Congestion issues were resolved by changing different floorplans and applying blockages.

Client : Intel India Private Limited 

Block name : Clkrx_pgd ( UX 4.1) Technology : Intel 7nm

Worked on block level RTL to GDSII implementation which includes floor-planning, power planning, Placement, CTS, Routing. Worked on Signoff flows extraction, timing (STA), Caliber violations, IR, LEC and LVS.

We faced challenges to place macros with proper module placement.

We faced congestion issues near IO ports, Congestion issues were resolved by changing different floorplans and applying blockages.

Worked on IR drop issues to fix the Static IR self-heat violations.

Client : Intel India Private Limited

Block name : Parmctrkddr ( QLC)

Technology : Intel 7nm

Worked on Parmctrkddr block where IP Configuration and PVT configuration was changed, resulting violations were observed and the partitions were made clean from Signoff.

Fixed all the Lv bundle issues , DRC fixing is quite challenging. Manually had to reroute so many nets to fix the Antenna violations.

Client : Intel India Private Limited 

Block name : pma_lane ( Display 3.0) Technology : Intel 7nm 

Worked on pma_lane TR phase, Need to reproduce the design which earlier was in RDT flow to the

cheetah flow and to replicate the block qor and to complete the signoff flows in cheetah flow. During project execution phase responsible for floorplan, placement congestion and route and all the signoff flows.

Implemented better floor plan, Created the bounds at placement to meet the timing and done the experiments with skew changes to bring the better timing and congestion.

Reduced the global and local congestion using blockages and cell padding.

Performed timing closure techniques such as creation of Bounds for critical Modules, Path Grouping.

Client : Intel India Private Limited

Technology : Intel 7nm)

Block name : apma_pll_wrapper. (UX 4P0)

Worked for DRC and LVS fixes for apma_pll_wrapper, manually fixed the twire missing issues and shorts and opens cleanup and fixed Antenna violations.

Fixed IR issues on few layers where the drop is higher by manually drawing the power grid.

Client : Intel India Private Limited

Technology : Intel 7nm

Block name : ip74pppxpllad_g4anatop (ADPLL)

Worked for ip74pppxpllad_g4anatop block DRC and LVS fixes Antenna violations and Supported in all the LV signoff Activities.

Client : Intel India Private Limited Technology 

Intel 10nm (Alder lake) Block name : Psftc4

Worked on synthesis using DC-Topographical.

Implemented useful skew techniques and address timing violations Worked on Physical verification fixes like DRC, LVS and Antenna.

Worked on FEV, VCLP and CALIBER (Intel specific flow) Worked on RV fixes like self-heat, S-Factor and EM violations

Client : Intel India Private Limited Technology 

Intel 14nm Polaris XG806 (HPG group) Block name : BPSS Pegasus (Sub System)

PNR flow : RDT

Responsible for block level synthesis from import design to finish stage and provide the inputs to the pnr. Block is having multiple power domains.

Working with upf team to resolve the low power issues.

Performed multiple experiments for better qor during the synthesis.