Design Verification Engineer with 1.7 years of experience in verifying complex IP and other complex systems using System Verilog (UVM). Experience in Perl and Shell Scripting. Experience in Verifying the memories by RAL model.
Development of complete VIP for AXI protocol and Test plan creation , developed the TB architecture and relevant test cases . Worked on Coverage closure using regression testing.
Development of complete VIP for Verification of AHB to APB bridge and developed the TB architecture and relevant test cases . Worked on coverage closure using regression testing
Development of VIP for RISCV processor . Worked on verifying the different commands. Used RAL model for writing and reading from the design . Generated different test case scenarios and close coverage using regression testing.
Trained many corporate candidates in System Verilog and UVM, Trained them in building the VIP for RISCV ,AXI and AHB