Summary
Overview
Work History
Education
Skills
Leanring Ahead
Timeline
Generic

CHALAM TIRUNAGARI

Summary

Design Verification Engineer with 1.7 years of experience in verifying complex IP and other complex systems using System Verilog (UVM). Experience in Perl and Shell Scripting. Experience in Verifying the memories by RAL model.

Overview

8
8
years of professional experience

Work History

Member of Technical Staff

Maven Silicon Soft Tech PvtLtd
08.2022 - Current
  • AXI VIP Development

Development of complete VIP for AXI protocol and Test plan creation , developed the TB architecture and relevant test cases . Worked on Coverage closure using regression testing.

  • Verification of AHB to APB Bridge

Development of complete VIP for Verification of AHB to APB bridge and developed the TB architecture and relevant test cases . Worked on coverage closure using regression testing

  • RISCV processor Verification

Development of VIP for RISCV processor . Worked on verifying the different commands. Used RAL model for writing and reading from the design . Generated different test case scenarios and close coverage using regression testing.

  • Training and Development

Trained many corporate candidates in System Verilog and UVM, Trained them in building the VIP for RISCV ,AXI and AHB


Assistant Professor

CVR College Of Engineering
02.2016 - 08.2022
  • Taught different subjects like Digital Logic Design , Verilog ,System Verilog and Control System
  • Guided many graduate and post graduate candidate to complete their projects

Education

M.Tech - VLSI System Design

JNTUH Hyderabad
Armoor, Nizamabad., Telangana
03.2015

B.Tech - Electronics And Communication Engineering

JNTUHyderabad
Nizamabad, India
06.2011

Skills

  • System Verilog UVM
  • Simulation tools: QuestaSim, Synopsys DVE, Verdi
  • RTL Design using Verilog
  • C and scripting using Python, Perl, Shell
  • AHB, AXI, APB protocols
  • Micro-processor architecture
  • SVA based Verification

Leanring Ahead

  • Started Learning PCIe protocol
  • Stated learning Gate Level Simulation
  • Stared Learning Machine Learning and Artificial Intelligence

Timeline

Member of Technical Staff

Maven Silicon Soft Tech PvtLtd
08.2022 - Current

Assistant Professor

CVR College Of Engineering
02.2016 - 08.2022

M.Tech - VLSI System Design

JNTUH Hyderabad

B.Tech - Electronics And Communication Engineering

JNTUHyderabad
CHALAM TIRUNAGARI