Chandrika Rani Musham
Summary
Physical Design Engineer with 5+ years of experience in the semiconductor industry, focusing on RTL to GDSII flow and timing closure. Proficient in DRC analysis and PnR implementation across various process nodes including 2nm, 3nm, 4nm, and 12nm. Demonstrated ability to optimize design processes and enhance performance metrics.
Overview
5
5
years of professional experience
Work History
Physical Design Engineer
Insemi technology Pvt Ltd (Qualcomm as Client)
Bangalore
12.2021 - Current
- Floorplan - Worked on HM-level heir designs with a high memory count.
- PnR - PnR implementation for high pin density HMs, pushed for 75% utilization, and multiple CTS trials for the best ID and skew.
- ECO - Performed ECO iterations for timing closure using DMSA flow, Powerwizz, and Tweaker, and was responsible for manually cleaning setup and hold for timing-critical paths. I wrote a manual ecos for cleaning timing DRCs.
- Worked on PV fixes, such as shorts, opens, antenna violations, DRVs, and PDN violations, including c2i, dynamic IR, signal EM, and power EM.
- Worked on CLP violations, such as undrivens, tie cell violations, and cross violations.
Physical Design Engineer
Insemi technology Pvt. Ltd (Synopsys as client)
Bangalore
09.2020 - 09.2021
- Performed a complete back-end flow, such as synthesis, floorplanning, power planning, CTS, and routing.
- Experienced floorplan issues, congestion in a few regions in the design, and able to resolve with different floorplan experiments, path grouping at the placement stage.
- Implemented CTS with minimum skew and latency. Created a skew group for a group of registers to meet the targeted skew.
- Succeeded in meeting design timing closure and DRCs in the ECO phase.
- Worked on Power EM and signal EM fixes.
Education
Bachelor of Engineering - Electronics And Communication Engineering
MVSR Engineering College (Affiliated To OU)
Hyderabad05-2018
Diploma - Electronics And Communication Engineering
Kamala Nehru Polytechnic For Women
Hyderabad06-2015
High School -
Brilliant Grammar High School
Miryalaguda, Nalgonda Dist05-2012
Skills
- Tools: Cadence Innovus, Synopsys ICC2
- Verification - Calibre (DRC, LVS, ERC, antenna)
- Timing/ECO: Primetime, Tweaker, PowerWizz, DMSA
- Scripting - Tcl
- Expertise: floorplanning, PnR, CTS, STA, PV, IR/EM, ECO implementation
Timeline
Physical Design Engineer
Insemi technology Pvt Ltd (Qualcomm as Client)
12.2021 - Current
Physical Design Engineer
Insemi technology Pvt. Ltd (Synopsys as client)
09.2020 - 09.2021
Bachelor of Engineering - Electronics And Communication Engineering
MVSR Engineering College (Affiliated To OU)
Diploma - Electronics And Communication Engineering
Kamala Nehru Polytechnic For Women
High School -
Brilliant Grammar High School