CHIRANJAN NAYAK K

• Worked on PNR of HTB block with ownership on ARM and NIC hierarchies including physical aware synthesis for IBM client. Met the required deadlines.

Design Specification

• 1 to 1.5Ghz Frequency with 4.8M instance count
• 5 nm low power design with 15 metal layers
• 355 macros and 21k ports

Challenges Faced

• Prects' timing violations
• Congestion issue as array connectivity was critical
• Certain flow issue causing high runtime in CTS

• Worked on Memory IP's for MediaTek client as direct contract

Design Specification

• 800Mhz to 1.2Ghz Frequency with max 2M instance count
• 2nm, 3nm, 7nm, 12nm design with metal layer ranging from 9metal layers to 15metal layers
• 40 SRAMS

Challenges Faced

• Critical congestion near the ports boundary
• DRV fixes
• Skew balancing issue as skew target was less

• Worked on Memory IP's for MediaTek client

Design Specifications

• 600Mhz to 1.6Ghz Frequency with max 3M instance count
• 2nm, 3nm, 5nm, 7nm, 12nm, 28nm design with metal layers ranging from 7 metal layers to 15metal layers

Challenges Faced

• Critical congestion as design was a very small sized
• IR-EM issue
• Metal ECO fixes after BTO
• Setup and Hold fixes

• Worked on modems and CPU's block for Intel FAB

Design Specifications

• 2.4Ghz Frequency with max 4M instance count and 17k ports
• 10nm, 10nm++, 14nm, 22nm, 28nm design with metal layers ranging from 7metal layers to 12metal layers

Challenges Faced

• Fixed the DRCs near hotspot region
• Antenna, ERC fixes in the design
• Crosstalk fixes which were impacting the timing
• LVS cleanup in the S3 level