Deepak Chamalla

SOC Functional Validation Engineer

Tessolve Semiconductor Pvt Ltd

Bengaluru

02.2022 - Current

Led post-silicon validation and debugging of DDR5/LPDDR5 memory subsystems, ensuring high performance and reliable operation.
Possesses extensive experience in memory IP subsystems under the uncore domain of CPUs.
Collaborated with design, MRC, EV (analog verification), and validation teams to validate higher memory speeds and new features.
Performed memory stress testing, corner case analysis, and margining to identify and analyze failures in silicon.
Utilized hardware and software debugging tools (logic analyzers, oscilloscopes, Trace32, JTAG, and firmware logs) for issue isolation and resolution.
Conducted silicon-level failure analysis to root-cause functional and performance issues, optimizing memory timing parameters, and power efficiency.
Developed custom test content using microcode patches, firmware modifications, and OS-level tools to validate specific IP interactions.
Reviewed design changes and their impact on validation coverage, adjusting validation strategies accordingly.
Executed validation test plans across multiple environments, including simulation, emulation, and FPGA prototyping, ensuring silicon readiness. Documented findings, debug methodologies, and issue resolutions to improve future silicon validation cycles.
Managed CCB requests from Alibaba, JIO, and AWS, with direct customer engagement.
Strong exposure to agile methodologies.
Developed solutions to debug failures encountered during automation.
Usage of PythonSV, bringing up the system from scratch with software collaterals.
Worked on multiple operating systems, such as SVOS, CentOS, Linux, Ubuntu, Red Hat, Windows OS, and VMware.
Skilled in utilizing system firmware (BMC, BIOS, and CPLD), and proficient with Quartus Prime and USB Blaster tools.