Diksha
Bengaluru
Summary
4 years of overall experience in system PDN, Die to Die signal routing along with SI/PI analysis of power rails , HBM, DDR and across high speed SERDES interface on interposer and packages.
Worked on design of various interposer,packages along with SI/PI analysis. Functions as part of dynamic cutting edge design team and played a critical role in 10+ successful tapeouts with SI/PI sign off. Well experience on high speed signal and PDN routing and optimization , bump planning , decap optimization for core/IO power domain, time domain and frequency domain analysis.
Overview
4
4
years of professional experience
Work History
ASIC Design Engineer II
Alphawave Semi
04.2024 - Current
- 3D IC Design and Analysis Engineer with deep understanding of packaging, design and analysis of silicon based interposer and integrated fan out organic substrates (InFO) .
- Experience in design and SI/PI analysis of HBM2E, HBM3 (8.4 Gbps), LPDDR (20 Gbps) , UCIE (24 Gbps) based interposers and package.
- Expertise in time domain and frequency domain simulations , PDN modelling and Crosstalk management with return path analysis for return loss.
- Submitted a patent on high speed interconnect in year 2024.
- Bump planning and finalization of various routing patterns based on SI/PI analysis to accommodate the desire speed.
- Deep Knowledge of Cadence Sigrity tools (Clarity 3D , PowerSI, TopXP) , Spectre Simulations , Allegro Package Design, Innovus, Ansys (HFSS, Raptor HX) , Keysight ADS
- Pre layout plan Analysis for decap requirement
- Decaps placement and optimisation
- Serdes interface routing optimisation and SI analysis
- Skilled at working independently and collaboratively in a team environment.
- Self-motivated, with a strong sense of personal responsibility
ASIC Design Engineer
Open Silicon
07.2020 - 09.2022
- Design of HBM2 and HBM2E based silicon interposers.
- Expertise in EM and transmission line theory , S-parameter extraction and suggestions on routing methodology based on signal loss factors and crosstalk.
- Time domain simulations (Analysis of Eye Diagram, Skew and Jitter).
- PDN modelling and Power integrity analysis.
- Collaborated with design teams on design reviews and validation testing of on chip simulations
Education
Master of Technology - VLSI
Dhirubhai Ambani Institute of ICT
Gandhinagar07.2020
B.Tech - Electronics And Communication
SRM University
Chennai 05.2018
Skills
Cadence Sigrity tools , Cadence Allegro , Innovus
Ansys HFSS , Keysight ADS, SPICE simulation
Experience in signalling speed upto 32Gbps
EM and transmission line theory
Knowledge of system level power integrity
Expertise in time domain and frequency domain simulation
Signal loss and crosstalk control
Hands on experience in scripting (Perl)
Deep understanding of S-parameters, eye diagram, IBIS model,skew and jitter
Bump planning, D2D routing and PDN routing
Timeline
ASIC Design Engineer II
Alphawave Semi
04.2024 - Current
ASIC Design Engineer
Open Silicon
07.2020 - 09.2022
Master of Technology - VLSI
Dhirubhai Ambani Institute of ICT
B.Tech - Electronics And Communication
SRM University
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