KANUGOVI HARINI
Bangalore
Summary
Seeking a challenging position in an esteemed organization where I can explore my skills in developing design and verifying by contributing towards the growth of organization.
Overview
3
3
years of professional experience
1
1
Certification
Work History
Graphics hardware DV engineer
Qualcomm India Pvt. limited
05.2022 - Current
Bucketized and debugged the errors for regressions of vectors and randoms, worked on xelium tool to make it compatible for our block
Associate Engineer
Cerium Systems Pvt. Ltd. (Client – Intel,End Client – Mobiveil)
04.2021 - 04.2022
Going through specifications, learning cache and memory related,observations and analysis of cache and memory using MESI protocol using CXL (Host as Intel processor and Mobiveil Device)
Education
Bachelor of technology - Electronics and communication engineering
Vignana Bharathi institute of technology (Affiliated to JNTUH)
Intermediate (MPC) - undefined
Sri Gayatri junior college
SSC -
Geetanjali Vidhyalaya School
Skills
Good communicator and have strong presentation skills
Certification
Professional training: PG Diploma in VLSI (Frontend Developer), Cranes varsity a Training Division of Cranes Software International Ltd, 08/01/19, 01/01/20, 5 months
Accomplishments
- Joint secretary at IETE – ISF SB for the tenure 2017-2018.
- Technical coordinator at IEEE – VBIT SB for the tenure 2017-2018.
- Document writer at IETE – VBIT SB for the tenure 2016-2017.
Technical Exposure
Verilog, System Verilog, UVM, Verdi (Synopsys), Verisium (Cadence)
Papers Published
Participated in International conference on emerging trends in engineering (ICETE) conducted by OUCE Alumni association with publishing partner Spinger at Osmania University., https://link.springer.com/chapter/10.1007%2F978-3-030-24318-0_21
Projects
Project-1: Graphic Processor Unit Verification, This is to verify Cache block in GPU for Vector and Random tests, basically this block is responsible for storing and making some decisions required for the other blocks inside GPC., Verdi (Synopsys), Verisium (Cadence), UVM, Debugger, May 2022 – Present Project-2: Compute Express Link (CXL) InterOp, This project is to verify the host which is integrated with five different devices. Need to check whether link is trained with Gen5 speed and debug the failure test cases., Verdi (Synopsys), UVM, Debugger, April 2021 – April 2022
Disclaimer
I hereby declare that the above information is true and correct to the best of my knowledge.
Timeline
Graphics hardware DV engineer
Qualcomm India Pvt. limited
05.2022 - Current
Associate Engineer
Cerium Systems Pvt. Ltd. (Client – Intel,End Client – Mobiveil)
04.2021 - 04.2022
Bachelor of technology - Electronics and communication engineering
Vignana Bharathi institute of technology (Affiliated to JNTUH)
Intermediate (MPC) - undefined
Sri Gayatri junior college
SSC -
Geetanjali Vidhyalaya School
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