

Accomplished Sr Design Verification Engineer with a proven track record at Qualcomm, enhancing verification processes using advanced simulation techniques. Expert in UVM methodology and adept at fostering team collaboration, significantly minimizing risks through strategic test implementations. Achieved notable success in Automotive Safety SoC Verification, demonstrating exceptional problem-solving and SystemVerilog expertise.
UVM methodology
Functional Coverage
Scripting languages proficiency
RTL design understanding
Gate-level simulations
Formal verification techniques
SystemVerilog expertise
Assertion-based verification
Coverage-driven verification
Power-aware verification