KRISHNABIR GHOSH

Power Management Unit [PMU] :

1. Working as System Power architect across multiple SOCs to achieve micro-idle management.

2. This required through analysis of traffic initiator transaction pattern and governing the windows to achieve micro-idle.

3. To come up with multiple PMU topologies across multiple SOCs.

4. Interaction with respective IPs POCs and capturing the detailed spec.

5. Micro-idle saving without affecting the system performance.

6. Chip durability increase due to reduction of leakage power and thus increases the DOU(Days of Usage).

7. Interaction with Global Clock controller(GCC) and Always on Sub-system (AOSS) to achieve different sleep modes.

8. Decision making based on Continuous inputs from Active clients and NOCs

9. Micro-architecture, Sequence Diagrams and RTL design

10. Active SOC, Platform and Silicon debugs.

System Memory Management Unit[SMMU]:

1. Worked as Premium tier flagship POC for SMMU across multiple chips.

2. Capturing requirement from clients and NOC for the data type, security state IDs, Bus protocol and additional details required for Translation Buffer Unit(TBU).

3. Micro-architecture and RTL design for TBU TLB Hazard, Low power, Autonomous clock gating.

4. APB based scan dump for SMMU to enable debug during hang scenario. Defining micro-architecture, defining CBDFT core boundary and interaction with DCC and DAP.

5. Designing the custom bridge interface for communication between TBU and NOCs.

6. Defining power and clock strategy for different chips depending on use case.

7. Active IP level, SOC level and Si level debugs.

8. Executed multiple ECOs over multiple chips in Base and Metal.

9. GLS Debugs

Project : Visual Display Channel (FFT/DFT Block)

Project Description: The main aim is to design a common architecture and provide the design for 3780/4725 DFT and 1k-32k FFT

Tools : Design Compiler, spyglass, irun, Cadence simvision

Platform : KANT ASIC chip.

Role and contribution :

1. Ownership of Independent module

2. To provide the micro-architecture document for the design.

3. Providing the proof of concept in C and MATLAB.

4. Provide both float and fixed point implementation in C and MATLAB.

5. RTL development of the design and synthesis of the design.

6. To run spyglass Lint for various checks.

7. Using perl and C to generate the test environment.

8. To help in UVM verification integration.

9. To provide detailed design document and presentation of proof of concept.

10. Verifying the outputs and comparing the estimated SQNR variation between the RTL and MATLAB Model.

Project : 1. Relay Station:Wimax16 e TDD & FDD (Oct 2011 – Aug 2014)

2. LTE L1(PHY) Development in FPGA(Aug 2014 – Feb 2015)

Project Descriptions: 1. It’s a WiMAX 16e based Fixed Relay system consisting of Master Relay and Mobile station. WiMAX 16e based Relay Communication System is designed to achieve coverage extension and capacity enhancement.

Relay system acts as both receiver and transmitter implemented on the same module(FPGA) . Base band and peripheral interface are developed on FPGA, Base band module which receives the digital packets from the DSP and generates

the wimax frame structures according to the wimax standard timing and transmits over the air, it’s also consists of SRIO interface design and CPRI interface design .

2. The project is aim for complete LTE L1 solution in FPGA. The model is generated using system generator. Four FPGAs are used, two for DL and two for UL. The communication between all the FPGAs is handled through SRIO interface. The FPGAs are communicating to L1 control software (GPP) through SRIO. The events and logging is Handled also through SRIO

Tools : Xilinx ISE 12.4, 13.4, Chipscope, Modelsim10.2 .

Platform : Virtex 5 LX155T, Virtex5 VLX110T, Virtex 5 XC5VSX95T

Role and contribution :

1. Architecture design for the Relay

2. RTL level VHDL and Verilog coding

a. Base Band development ( Base & Mobile Station )

b. CPRI Interface (Radiocomp and Signalion Radio)

c. Complete Vendor Specific Module for interfacing with Signalion radio.

d. SRIO Interface

3. Ownership of Independent L1 modules for DL and UL.

4. Merging the codes using system generator.

5. Functional Simulation for the entire system.

6. Carrying out the various test cases and verifying with the expected MATLAB dumps.

7. Handling the Events and Logging to the L1 control software.

8. Responsible for initial configuration support for all the FPGAs.

9. Functional simulation using model sim

10. Synthesis & and On-chip verification using Chipscope

11. Timing analysis and real time validation in the boards

12. Unit and System Integration testing