Lokesh Soni

UCIe Designs:

TSMC N3p

• Leading Team of 3 people, Analyzing work done by team for all block.
• Developed & Integrate flow to pipeline with Company Central flow, improving output quality and sanity checks.
• Integrating Analog IO's which are responsible for data traffic on Lanes.
• Setting standardization for Input handshake with Different teams & standardizing Vectors generated for specific pattern to avoid any dispute in power no's.
• Regular feedback for PD Team to fix PG grid in order to encounter demand current.

TSMC 3nm

• Introduced to UCIe design, Get setup ready for power signoff
• Get regular EMIR analysis done at 24 Gbps.
• Understand architecture and get Different pattern Vectors for testing.

Samsung S4X

• Understand Samsung library to get balance for Timing and Power
• Introducing Redhawk-SC tool from Ansys for Signoff.
• Setup flow for Samsung technode and testing rigorously.
• Analyze for design changes and provide feedback.
• Optimized project workflows, leading to reduced turnaround times and increased productivity.

HBM Design:

TSMC 3 nm - 4 Channel - 2.5D design

• Signoff EMIR at high speed 8.4 Gbps, 4+ Ghz clocks with Cadence tools
• Understanding HBM architecture to analyze different scenarios with accuracy.
• Analyze EM and Voltage drop at different corners.
• Understanding Vectors for design to get different scenario power.
• Get die model to integrate with 2.5d Interposer design.
• Analyzing each channel for Grid Sanity, TPAD testing.
• Dealing with analog blocks for Memory operations, clock generators.
• Coordinates with Different teams for different sets of inputs and get work done.

TSMC 5 nm - 8 Channel, 2.5d Design

• Introduced to Power Signoff domain, Headstart with IR signoff in Cadence tools
• Creating Entire flow for Power Signoff for Static & Dynamic analysis
• Tapeout with high speed design at 7.6 Gbps, 3.6 Ghz.
• Looking Deep into analog blocks to capture corner case IR issues.
• Sanity check for Bump Currents, Rail Cap, PG EM, Inputs, Grid robustness, Cap & Current density, Clock Gating, VCD/Power Coverage.
• Coordinating with Teams for Grid stability, controlling HBM Phy power.

Samsung 4nm

• Fixed Timing on high density design with 2M+ inst at 1.2 Ghz
• Engaged with Pegasus as ISC Flow for Power solutions
• Hands on with STA to analyze timing with Cadence tool

Samsung 10nm

• Fixed Timing on high density design with 1M+ inst at 1 Ghz
• Building Spine clock tree to reduce insertion delay and minimize skew
• Engaged with Pegasus to address metal fill timing jump at implementation stage
• Introducing ISC timing closure within implementation stage
• Hands on with STA to analyze timing with Cadence tool

Samsung 14nm

• Physical Implementation of multiple block at Main frqn 1 Ghz
• PPA push for blocks to increase cadence footprint, introducing STA for eco cycles.
• Introducing M.S clock tree to reduce insertion delay and Implemented Spine clock structure

Intel Project at 14nm Technode

• Examined Pointed issues in UPF for multiple blocks which includes correction of different power strategy's in upf
• Generate Functional ECO's to implement in design
• Implementation of the design which includes strategic placement and routing critical nets which stagnated on sides of macros and need to address manually at pre-cts stage

Samsung Project at 8nm

• Implementation of the design till CTS, Analyzing Memory timing paths.
• Power Via modification script resolve congestion on Power Mesh
• Automate region for pipeline flop placement to address custer region issue.
• Understand Module structure in synthesis to reduce data depth and tweak sdc for PnR input netlist

Samsung Project at 14nm

• Physical Implementation of blocks majorly to reduce clock insertion delay through building spine clock
• Implemented customer buffer methodology to address issues in powerDomains
• Created bus routing for Dense pin memories to control timing & congestion
• Handle routing congestion
• Generated ECO's for multiple blocks