SURAJ BHALERAO
Manchar
Summary
Results-driven CPU Physical Design Engineer with 8+ years of experience in EMIR sign-off, power integrity, reliability, and physical verification at advanced technology nodes. Proven expertise in full-chip and block-level physical design, power grid optimization, and tape-out sign-off, delivering robust, manufacturable designs across high-volume SoC products.
Overview
7
7
years of professional experience
Work History
CPU Physical Design Engineer
Intel Technology India Pvt Ltd
Bengaluru
07.2017 - 11.2024
- Led full-chip and block-level EMIR sign-off, Joule heating, and thermal analysis using RedHawks-SC, ensuring compliance with foundry and reliability limits.
- Performed early-stage EMIR feasibility analysis to influence floor planning and power grid strategy.
- Improved EMIR margins through cell spreading, decap insertion, routing optimization, and metal/via enhancements.
- Executed static and dynamic IR drop analysis (vector-based and vectorless) for critical power domains.
- Collaborated closely with PD, STA, and power teams to deliver timing-safe EMIR ECOs.
- Drove hierarchical data path blocks and full-chip layout convergence, including placement, routing, physical verification, RV, and extraction through sign-off.
- Designed complex physical layouts for integrated circuits and semiconductor devices.
- Developed and maintained design documentation for multiple projects simultaneously.
- Mentored junior engineers on best practices in physical design techniques.
Education
Master of Science - Electronic Science
University of Pune
Pune06-2015
Skills
- EMIR sign-off (static and dynamic IR drop, EM, Joule heating, thermal)
- Power grid design and optimization
- Vector and vectorless IR analysis
- Full-chip and block-level physical design
- Physical verification (DRC/LVS) and extraction
- Timing-safe EMIR ECO implementation
- Layout convergence
- Technical documentation
- Problem solving
- Team mentoring
Tools & Technologies
- RedHawk-SC, Totem: IR, EM, thermal
- Synopsys: ICC2, StarRC, IC Validator
- Intel proprietary physical design and sign-off tools
- Technology nodes: Intel / TSMC – 14nm, 10nm, 7nm, 5nm
Accomplishments
• Achieved first-pass EMIR sign-off on high-volume CPU/SoC products
• Reduced peak dynamic IR drop by ~25% through targeted power grid optimization
• Closed critical EM violations on clock and power routes without timing regressions
• Successfully completed 6 tape-ins, including 4 PRQs, across 14nm, 10nm, and 7nm nodes
• Delivered waiver-free PV & RV sign-off on multiple projects
• Recognized for exceptional commitment to RV sign-off and tapeout execution
• Awarded for custom layout design and physical verification excellence
• Reduced peak dynamic IR drop by ~25% through targeted power grid optimization
• Closed critical EM violations on clock and power routes without timing regressions
• Successfully completed 6 tape-ins, including 4 PRQs, across 14nm, 10nm, and 7nm nodes
• Delivered waiver-free PV & RV sign-off on multiple projects
• Recognized for exceptional commitment to RV sign-off and tapeout execution
• Awarded for custom layout design and physical verification excellence
Languages
English
Proficient (C2)
C2
Hindi
Proficient (C2)
C2
Marathi
Native
Native
Timeline
CPU Physical Design Engineer
Intel Technology India Pvt Ltd
07.2017 - 11.2024
Master of Science - Electronic Science
University of Pune