Krati Agrawal
Bengaluru
Summary
Digital Design Engineer with 5 years of experience in various physical design domains. Proficient in layout design, EM/IR sign-off, PDN/RV, and static timing analysis (STA). With a strong engineering background, complemented by a postgraduate degree in the VLSI domain from NIT Jaipur, I am looking for opportunities to leverage my knowledge and skills. Quick learner with a track record of adapting to changing environments.
Overview
6
6
years of professional experience
Work History
Physical Design Engineer - STA & Synthesis
Intel Technology INDIA Pvt Ltd.
Bengaluru
06.2024 - Current
- Knowledge in RTL, to netlist handoff, to the physical design team.
- STA Experience on low-power node technologies.
- Understanding on STA concepts, constraints, and sign-off.
Power Delivery Engineer
Intel Technology INDIA Pvt Ltd.
Bengaluru
07.2022 - 05.2024
- Responsible for efficient Power Delivery & Reliability Verification at full-chip for Intel P-cores.
- Expertise on static and dynamic IR drop analysis (Full Chip & block level), pre and post thermal analysis, signal and power EM analysis.
- Power grid design for both front-side and backside power delivery.
Digital Design Engineer
Intel Technology INDIA Pvt Ltd.
Bengaluru
07.2020 - 06.2022
- Worked as a layout owner, responsible for the integration of blocks in 14nm, 10nm, and 7nm process nodes without compromising timing and PPA, along with experience in converging multi-voltage dense clusters.
- Hands-on experience with layout/physical design, timing, and power convergence.
- Collaborated closely with team members, and cross-site, cross-functional teams to achieve project objectives and meet deadlines.
Physical Design Intern
Intel Technology INDIA Pvt Ltd.
Bengaluru
06.2019 - 06.2020
- Part of 'CORE GROUP' which develop processor cores.
- Role involves floor planning, routing, develop algorithm to meet timing, area and power goals using placement and routing tool, TCL.
Education
M.Tech. - VLSI Design
Malaviya National Institute of Technology
Jaipur01.2020
B.Tech. - Electronics Engg.
Institute of Engineering And Rural Technology
Allahabad01.2017
Diploma in Engineering - Information Technology
Aligarh Muslim University
Aligarh01.2014
High School - CBSE
Rajni Public School
Dibai01.2011
Skills
- Floorplanning & Place-and-Route (PnR)
- Static timing analysis
- RV/IR Sign-off, Thermal Analysis
- TCL automation
- UNIX/Linux Command Line
- Tools: Primetime, Fusion Compiler, RedHawk
Projects
- Routing optimization of VLSI layout for delay reduction, M.Tech project
- Design and Simulation of MEMS Capacitive Pressure Sensor - M.Tech Project
- Vehicle Accident Alert System - B.Tech Project
- University Voting Management System - Diploma in Eng. Project
Achievements And Activities
- Qualified for GATE 2018 in Electronics and Communication Engineering, with a 98.29 percentile
- Participated in a one-week program on 'Mixed-Signal CMOS ICs - Methodology of Circuit to Chip Design' under the aegis of the Electronics and ICT Academy, MNIT Jaipur
Timeline
Physical Design Engineer - STA & Synthesis
Intel Technology INDIA Pvt Ltd.
06.2024 - Current
Power Delivery Engineer
Intel Technology INDIA Pvt Ltd.
07.2022 - 05.2024
Digital Design Engineer
Intel Technology INDIA Pvt Ltd.
07.2020 - 06.2022
Physical Design Intern
Intel Technology INDIA Pvt Ltd.
06.2019 - 06.2020
M.Tech. - VLSI Design
Malaviya National Institute of Technology
B.Tech. - Electronics Engg.
Institute of Engineering And Rural Technology
Diploma in Engineering - Information Technology
Aligarh Muslim University
High School - CBSE
Rajni Public School
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