Summary
Overview
Work History
Education
Skills
Websites
Technologies Tools
Interests
Timeline
Generic
Navaneeth Anand

Navaneeth Anand

Senior Physical Design Engineer
Bengaluru

Summary

More than 4 years of enriched experience in Physical Design with multi-million gate design tape-outs.

Experience in leading Engineers in multiple projects.

Independent Execution of Synthesis, P&R (PnR) & all sign-off checks (STA, EMIR, LEC, LVS & DRC).

Expertise in Timing Analysis, Timing Closure & Advanced STA concepts.

Experience in Clock Spine Implementation for best latency and skew.

Expertise in Congestion Analysis and Clock Tree Synthesis.

Strong experience and knowledge in TCL, VIM & Unix.

Good knowledge in Synthesis, Floor Planning, Placement, Routing, EMIR, LEC and PV.

Overview

5
5
years of professional experience
3
3
Languages

Work History

Physical Design Engineer

Tech Mahindra Cerium
10.2019 - 09.2023

Worked on 7nm to 40 nm technology nodes.

Worked as a Lead Engineer for multiple project.

Experience in working as a Physical Design Engineer on individual as well as team projects.

Worked as an STA engineer on Full Chip, Subsystem and block level.

Experience in developing SDCs for Full Chip and individual blocks.

Experience in Full Chip partitioning, Bump planning, P&R (PnR) and all Sign Off checks.

Strong experience in TCL, VIM and Unix.

Worked on creating flow for MMMC STA and PnR

Worked on Synopsys and Cadence tools.



Senior Physical Design Engineer

BluLegion Technologies
09.2023 - Current

Worked on Samsung 4nm technology.

Expertise in CTS and Clock Spine building for best latency and skew.

Advanced experience and knowledge in Timing and Congestion analysis.

Expertise in Cadence tools for Physical Design.

Education

Bachelor of Technology - Electronics & Communications Engineering

TKM College of Engineering
Kollam, India
04.2001 -

Skills

STA

Technologies Tools

Technology Nodes: Samsung 4nm | Intel- 7nm &10nm | TSMC - 28nm

Tools Used: Fusion Compiler, ICC II, Innovus, PrimeTime, Tempus, Redhawk, Voltus, Design Compiler, Genus, Formality, Conformal , StarRC, QRC, Calibre, IC Workbench, TCL, VIM, Unix

Interests

Technology

Yoga

Travelling

Timeline

Senior Physical Design Engineer

BluLegion Technologies
09.2023 - Current

Physical Design Engineer

Tech Mahindra Cerium
10.2019 - 09.2023

Bachelor of Technology - Electronics & Communications Engineering

TKM College of Engineering
04.2001 -

Similar Profiles

CREATE PROFILE
Navaneeth AnandSenior Physical Design Engineer