GADILLI SAI NIKHIL

Physical Design Engineer with strong background in designing and implementing integrated circuits. Specialized in digital design, physical layout designs, and system-on-chip (SoC) engineering. Strengths include keen problem-solving capabilities, exceptional knowledge of ASIC design flow and EDA tools, and ability to work effectively within cross-functional teams. Proven record of improving efficiency in chip layout planning processes at previous positions.

Project3: (Role: Block Owner)

• Technology: 3nm; Tools used: Fusion compiler, Primetime, VCLP, LEC and Calibre.
• Design type: VA & VDCI tiles with 4 M instance count each along with high Macro Count in VA tile.
• Created Voltage regions during floorplan stage honoring UPF. Verified power grid generation.
• Done proper floorplan to meet timing, to have less congestion and util hotspots.
• Analyzed timing after every experiment and tried with different techniques like Grouping, Path margins, Cell padding/Split blockages to meet better timing QOR.
• Tried different CTS experiments like Early/Late Skewing to meet better Skew & latencies both for tile internal and FCT QOR.
• Implemented VA tile in Industry flow to utilize future placement knowledge at Floorplan stage to create AON regions all over the tile.
• Fixed Phyv and VSI violations using flow conventional techniques and scripts to meet signoff constraints.
• Executed ECOs with proper usage of single and dual rail cells. Created new AON region after all grid generation and signal routing done.

Project2: (Role: Block owner + Flow task)

• Technology: 3nm; Tools used: Fusion compiler, Primetime, VCLP, LEC and Calibre.
• Design type: DFP tile with 2 Power domains having 2 M instance count.
• Performed analysis regarding timing violations at different stages using Linux,Sed and Awk commands.
• Written tune files for various experiments conducted on this tile like magnet placement, Path grouping, skewing and sink assignment.
• Understood power gating low power technique in recent node technologies and gone through Power gating flow in AMD Tilebuilder Flow and educated my team regarding this.
• Performed flow related tasks like creating and releasing flow label for all milestones, worked with other teams like FM, VSI, IREM, FCFP and PHYV to execute their requirements and feedback in flow.
• worked with tile owners/leads of different containers to implement their IP specific requirements in flow like implementing specific VT type clock path, implementing merge flow, enabling pseudo merge flow & fast path flow, enabling specific MMMC setup for Ips.
• Constantly worked with CAD team to solve different flow blockers/issues faced by tile team during their PNR execution. written different scripts to help tile team to execute their tile specific requirements smoothly.

Project1: (Role: Block Owner)

• Technology: 5nm; Tools used: Fusion compiler, Primetime, VCLP, LEC and Calibre.
• Design type: DFP tile with 2 Power domains having 800 K instance count.
• Utilized both industry and hybrid DFP flows to run through the PnR targets for the tile and compared trails to conclude one final recipe for the tile.
• Written various scripts in TCL and Unix to implement tile specific requirements.
• Responsible for timing, PV and IR closure at ECO stage.

• Played a critical role in 3 nm AMD project where I need to setup the flow for tile level PNR task.
• I received appreciation from the client team for taking responsibility during critical times of project execution
• Published a technical paper in IEEE access entitled 'A secure and decentralized Blockchain based energy trading model using smart contract in V2G Network'.
• Stood as one of the very few members in the college to get merit scholarship in the academic year 2019-2022.

• Interested to learn new things
• Emerging technologies
• Learning about ancient theories
• Playing Table tennis and Badminton

• Quick Learner
• Creative with good Interpersonal Skills
• Hard worker
• Organizer

In light of the aforementioned, I kindly ask that you grant me the chance to serve in the aforementioned capacity within your esteemed organization. I will be extremely appreciative of this gesture. I hereby attest that, to the best of my knowledge and belief, the information and details provided above are accurate and true.