Summary
Overview
Work History
Education
Skills
Accomplishments
WORK SYNOPSIS
CAREER VISION
Timeline
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Manvith M Kuruva

Manvith M Kuruva

Bengaluru

Summary

Dynamic Physical Verification Engineer and Manager with 14 years of experience, excelling in SoC project leadership and critical block analysis. Proven expertise in EDA tools like Calibre and a strong ability in employee engagement. Successfully managed multiple projects, ensuring timely tapeout signoff and fostering collaboration between teams and foundries.

Overview

14
14
years of professional experience

Work History

Senior Staff/Manager

Qualcomm
Bengaluru
01.2016 - Current

Mirafra Technologies

Physical verification engineer
Bengaluru
11.2014 - 01.2016

Project Engineer

Wipro Technologies
Bengaluru
07.2011 - 11.2014

Education

Master of Technology -

BITS PILANI
07-2014

Bachelor of Engineering -

BNMIT
BENGALURU
03-2011

DVS COMPOSITE PU COLLEGE
SHIVAMOGGA
04-2007

Govt High School
Honnali, Davanagere
03-2005

Skills

  • SOC PV/HMPV run setup and tapeout signoff
  • Soc and HM project leading
  • Critical block analysis and sign-off
  • Technical issue debug, and guidance
  • Foundry manager, a bridge between Qualcomm and foundry
  • Expertise in EDA tools such as Calibre, FC, Innovus, ICW
  • Diverse technology node experience(till 2nm)
  • Third-party final sign-off
  • Employee engagement
  • Recruitment support
  • Workforce planning
  • Performance coaching

Accomplishments

  • Awarded Best Technical Paper Presentation at the prestigious Qbuzz 2023.
  • Honored with the Impact Award from the VP for successfully leading two complex projects simultaneously, demonstrating exceptional efficiency and leadership.
  • Led a high-performing team that earned the Best Team Award for excellence in project execution and collaboration
  • 200+ THANKQ points, Qualstar, best team player awards
  • Received multiple accolades from the global tapeout operations team for excellence in managing diverse tapeouts with precision and efficiency

WORK SYNOPSIS

PV expertise

  • Extensively engaged in verifying the physical integrity of complex SoC designs, HMs, ensuring precision and reliability with checks including DRC, ERC, SC, LVS, ANTENNA, and DFM
  • Driving the execution of a complex hard macro subsystem with a multi-level hierarchy, optimizing design efficiency, and resolving congestion challenges to ensure seamless integration
  • As a SoC PV lead, I have orchestrated verification strategies across advanced technology nodes, ensuring precision, efficiency, and seamless tapeout success
  • This role requires meticulous planning, sharp attention to detail, and a thorough evaluation of every element—from initial setup to final results.
  • As an HM lead, I have ensured hard macros are signoff-ready, optimizing their quality and reliability for seamless integration into the SoC
  • This role involves finalizing all physical verification checks while diligently overseeing database integrity throughout the entire process—from floorplan to tape-out
  • As a Foundry Manager, I have ensured the quality and integrity of the tapeout database by verifying layer completeness, performing critical pre-transfer checks, and guaranteeing seamless foundry handoff
  • Seamless collaboration across PV, PD, IP, RDL, Process, and Package teams has been the cornerstone of my success

Efficiency improvements

  • As a PV lead, I have consistently driven innovation to enhance execution methodologies, streamline workflows, and elevate overall system efficiency
  • We successfully implemented extensive automation across the system, earning widespread recognition from management for its efficiency and transformative impact

Team management

  • As a people manager, I am responsible for overseeing engineer goal tracking, providing strategic guidance, and conducting performance appraisals to foster growth and excellence
  • I oversee strategic resource planning, accurate scheduling, and effort estimation for PV closure, while actively contributing to the hiring process as part of the interview panel

CAREER VISION

In essence, my passion lies in harmonizing innovation with precision to drive the seamless execution of advanced semiconductor designs.

Timeline

Senior Staff/Manager

Qualcomm
01.2016 - Current

Mirafra Technologies

Physical verification engineer
11.2014 - 01.2016

Project Engineer

Wipro Technologies
07.2011 - 11.2014

Master of Technology -

BITS PILANI

Bachelor of Engineering -

BNMIT

DVS COMPOSITE PU COLLEGE

Govt High School
Manvith M Kuruva