Summary
Education
Skills
Projects
Positions Of Responsibility
Languages
Hobbies and Interests
Disclaimer
Timeline
Generic
Mohit Mehra

Mohit Mehra

Summary

Motivated student eager to apply classroom knowledge to real-world experiences, with a strong willingness to learn and contribute. Effective communicator with a collaborative mindset, ready to bring fresh perspectives and a strong work ethic to any team.

Education

B.Tech - ECE

Indraprastha Institute of Information Technology Delhi
New Delhi, India
06-2026

CBSE - Vasundhara Enclave, Delhi

Dashmesh Public School
Vasundhara Enclave, Delhi
03-2022

CBSE - Vasundhara Enclave, Delhi

Dashmesh Public School
Vasundhara Enclave, Delhi
03-2020

Skills

  • Verilog
  • RTL design
  • CMOS design
  • Logic design
  • DFT
  • Scan Chain Insertion
  • Timing analysis
  • Power optimization
  • Cadence Virtuoso
  • Cadence Genus
  • Innovus
  • Yosys
  • LTSpice
  • Vivado
  • Matlab
  • EagleCAD
  • Memory testing
  • Python
  • SQL
  • Linux
  • Cross-Functional Collaboration

Projects

PPAS-Based Evaluation of Multipliers | (Jan,2025 - Dec,2025)                                                       

(Works as an Undergraduate Researcher) 

  • Designed and evaluated radix multiplier architectures in Verilog, focusing on PPAS (Power, Performance, Area, Sustainability) metrics using industry-standard EDA tools under varied PVT conditions.
  • For larger bit-widths, Radix multipliers offer the lowest power and best sustainability, making them suitable for ML accelerators, encryption, and edge-AI.

Optimization of Clock Tree Network for Power Reduction | (Jan,2025 - May,2025)                

  • Investigated and implemented low-power Clock Tree Synthesis (CTS) techniques for a RISC-V processor using Cadence tools.
  • Benchmarked multiple CTS approaches and optimized the clock network to enhance power efficiency, reduce skew, and improve timing performance, achieving a 10% reduction in power and 9% area savings through strategic buffer reduction.

Boolean Operation implementation in 8T SRAM | (Jan,2025 - Apr,2025)                        

  • Designed and simulated an 8T SRAM-based in-memory computing cell to perform NAND and NOR logic, addressing read disturb issues for enhanced stability and energy efficiency.

OAI 32 Static CMOS Design | (Aug,2024 - Nov,2024)                                                                         

  • Designed and optimized an OAI32 gate in Cadence Virtuoso (schematic, layout, simulation). Analysis showed that non-complex designs had higher static/leakage power and area, with a slight increase in dynamic power.

Positions Of Responsibility

  • NXP Semiconductors - Supported operations for the NXP AIM India.
  • ASTRA - Supported operations for student-led tech fest.
  • E-Summit - Helped coordinate IIIT-Delhi's entrepreneurship summit.
  • 1 Pixel Design Conference - Assisted in organizing design-focused sessions.
  • ODYSSEY - Contributed to event logistics during annual cultural fest.

Languages

English
Advanced (C1)
C1
Hindi
Native
Native
Punjabi
Upper Intermediate (B2)
B2

Hobbies and Interests

  • Passionate about Cricket
  • Enthusiastic about watching movies and science fiction series

Disclaimer

The above information is correct to the best of my knowledge.

Timeline

B.Tech - ECE

Indraprastha Institute of Information Technology Delhi

CBSE - Vasundhara Enclave, Delhi

Dashmesh Public School

CBSE - Vasundhara Enclave, Delhi

Dashmesh Public School
Mohit Mehra