P Bhadra

Client: ARM

• Executed RTL integration and validated through LEC.

Client: Xilinx/AMD

Project 3: SoC Design Telluride Device T40

Duration: 2024 July to June 2025

• Managed RTL design quality control flows, ensuring compliance with Xilinx/AMD standards.
• Developed constraints for clock domain crossing analysis to enhance design integrity.
• Analyzed RTL performance assessment reports for SCGE and DCGE, identifying areas for optimization.
• Handling flow setup for CLP/UPF & analyzing the results.

Project 2: SoC Design Telluride Device T50

Duration: Sept 2023 to Feb 2024

• Managed RTL design QC flows for CDC, RDC to ensure compliance.
• Developed and debugged constraints for CDC, RDC, GCDC, achieving signoff on violations.
• Identified and resolved RTL lint violations through updates, ensuring design integrity.

Project 1: SoC Everest Gen – II.

Duration: 2022 August to 2023 July

• Writing CDC constraints based on RTL design and understanding clock / reset domains.
• Developed constraints for CDC and RDC, ensuring compliance for signoff and effective debugging of violations.
• Addressed flagged CDC violations and fixed them using valid synchronizer techniques.
• Managed RDC to prevent metastability during reset de-assertion.
• Updated waiver and control files for invalid CDC and RDC violations.
• Checking RTL Lint Violations and getting them fixed through RTL update.

Client: terminuscircuits

Duration:May 2018 - Dec 2021

• Project 1: Debug Trace Fabric Packetizer. This IP is used to capture IP hardware signals, packetize them with source clock timing.
• Configured clock domain crossing (CDC) setups and performed analysis and fixes.
• Identified and resolved RTL lint violations through necessary updates.
• Project 2: RCD. This SOC will use a second-generation enhanced 10 nm process called '10 nm+'. 10 nm+ will feature higher performance through higher drive current for the same.
• Set up and analyzed CDC, implementing fixes to ensure signal integrity.
• Configured lint setups and conducted analysis and fixes for design errors.
• Project 3: Flexbus LogPhy IP. The logical sub-block has two main sections a Transmit section that prepares outgoing information.
• Passing the Data Link Layer for transmission by the electrical sub-block, and a Receiver section that identifies and prepares received information before passing it to the Data Link Layer.
• Configured and analyzed Lint setup, addressing violations to enhance code quality.

Client: Apollo Micro Systems Ltd Hyd

Duration:May 2018 to July-2019

Project 1 : MIGM (Mining’s DRDO project) The board contains ADCs, DACs, NAND flash, NOR flash have to give data to microcontroller based on address and data lines between FPGA (KINTEX-7) and PROCESSOR.