Playing Cricket, Travelling
P Rakshith
Bangalore
Summary
Seeking an opportunity to work as a Physical Design Engineer in an innovative environment where I can utilize my technical knowledge and expertise to develop creative solutions.
Overview
2
2
years of professional experience
3
3
Languages
Work History
Interim Engineering Intern
Qualcomm
Bangalore
08.2024 - 06.2025
- Gained hands-on experience in various engineering tools, software, and techniques to contribute effectively to the projects.
- Developed and maintained project documentation, ensuring all team members had access to current specifications and designs.
- Handled 2 blocks with and without macros and ensured that it met all the parameters to the sign-off stage.
- Identified and resolved floorplan-stage issues such as low utilization and insufficient power domain coverage by strategically adding blockages and optimizing power domain utilization, ensuring successful transition to the placement stage in PNR.
- Resolved long net issues during the PNR stage by inserting buffers and breaking the nets to meet timing and routing constraints.
- Performed sign-off checks including Formal Verification, Conformal Low Power, Physical Verification, Grid Checks, and GAtekeeper Checks; identified and resolved issues such as shorts, opens, unconnected nets, overlaps, DRC violations, and spacing rule violations.
- Implemented STA-driven ECOs to address setup and hold violations, and manually generated ECOs to reduce TDRC violations including max transition, max capacitance, and test/func issues by applying techniques such as buffer insertion, fanout splitting and net splitting.
Graduate Trainee Engineer
RV-SKILLS Centre for Emerging Technologies
Bangalore
05.2023 - 09.2023
- The aim of this project was to deliver a good functioning tape out which met the IR drop, with less routing congestion and minimal setup and hold violations. It was also designed in such a way that, it helped us understand the concepts clearer.
- Meeting the IR drop issue- wherein small variations in the width and spacing of metal layers would result in shoot up of IR drop.
- Routing Congestion- sometimes small gap given between the macros to solve the congestion would result in much more higher congestion.
- Timing violations- analyzing the setup and hold violations after CTS and then finding out the root cause for the issue.
- Tools: SYNOPSYS(ICC2) TOOL
Education
Master of Technology - Vlsi Design And Embedded System
Ramaiah Institute of Technology
04.2001 -
Advanced Diploma - ASIC Design - Physical Design
RV-VLSI Design Center
Bangalore 01.2023 - 12.2023
Bachelor Degree - Electronics and Communication
Sir M Visvesvaraya Institute of Technology
01.2022 - 12.2022
12th - undefined
Vidya Mandir Ind. PU College
01.2018 - 12.2018
SSLC - undefined
Little Lilly's English Public School
01.2016 - 12.2016
Skills
SYNOPSYS(ICC2) Tool
Manual placement of macros
Floorplanning
IR drop analysis
Routing Congestion
Interests
Timeline
Interim Engineering Intern
Qualcomm
08.2024 - 06.2025
Graduate Trainee Engineer
RV-SKILLS Centre for Emerging Technologies
05.2023 - 09.2023
Advanced Diploma - ASIC Design - Physical Design
RV-VLSI Design Center
01.2023 - 12.2023
Bachelor Degree - Electronics and Communication
Sir M Visvesvaraya Institute of Technology
01.2022 - 12.2022
12th - undefined
Vidya Mandir Ind. PU College
01.2018 - 12.2018
SSLC - undefined
Little Lilly's English Public School
01.2016 - 12.2016
Master of Technology - Vlsi Design And Embedded System
Ramaiah Institute of Technology
04.2001 -