Summary
Overview
Work History
Education
Skills
Websites
Accomplishments
Timeline
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Parvathy G

SoC Debug Engineer
Bangaluru

Summary

Self-motivated and results-driven SoC Validation Engineer with 8+ years of experience in pre- and post-silicon validation, driver development, and complex system debugging. Proven expertise in developing innovative methodologies such as freeze-and-dump for scan cells and memory arrays, building Python frameworks for SoC register access, and leveraging pre-silicon emulation to identify issues early. Adept at managing multiple projects under tight deadlines, leading risk assessments, mentoring teams, and driving cross-functional collaboration to enhance system reliability and reduce time-to-market.

Overview

9
9
years of professional experience

Work History

SoC Validation Engineer

Intel
06.2019 - Current
  • Developed and implemented a freeze-and-dump methodology for MUXD scan cells and MBIST memory arrays across multiple projects, enabling efficient root cause analysis of RTL, hardware, and firmware bugs.
  • Designed and supported PythonSV, a Python framework that enables access to domain-level registers within SoC by leveraging statically generated TAP link network hierarchies.
  • Worked on pre-silicon emulation models to identify RTL and integration bugs ahead of silicon power-on, enabling early issue detection, and reducing bring-up time.
  • Managed multiple silicon validation projects concurrently under tight deadlines, led risk assessment meetings, and provided critical input on system impact, component criticality, and other key factors.
  • Mentored junior engineers in best practices for validation engineering methodologies, enhancing overall team capability and technical proficiency.
  • Assisted in creating a centralized repository for validation documents, streamlining access, and improving knowledge management for current and future projects.
  • Collaborated cross-functionally with design, firmware, and core teams to resolve complex issues, resulting in reduced downtime, and improved system reliability.
  • Created and conducted training sessions and boot camps for domain teams, enhancing expertise in validation methodologies and best practices.

Driver Development Engineer

Intel
09.2017 - 06.2019
  • Developed a feature to enable global timestamping across all domains in the modem project, improving event correlation, and debugging accuracy.
  • Handled platform services such as Boot and Mode Manager modules, ensuring smooth and reliable modern booting procedures.
  • Participated in performance improvement activities for modern device drivers, resulting in better system throughput, and reduced latency.

Graduate Technical Intern

Intel
07.2016 - 07.2017
  • Worked on developing a phone simulator framework for the Radio Interface Layer (RIL) in OFONO.
  • Sim Tool Kit feature implementation for cellular modem for OFONO.
  • Gained an in-depth understanding of the serving cell agent and cellular communication functionalities, including their implementation within the OFONO framework.

Education

Master of Technology - Computer Science

VTU (BMS College of Engineering)
Bengaluru, India
04.2001 -

Skills

Scan methodology (MUXD and MBIST)

C/C/OOPS Concept

Python

JTAG/ iJTAG

Verilog

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Accomplishments

  • Received multiple DRA (Divisional Recognition Awards) for outstanding contributions to silicon validation, methodology development, and cross-functional collaboration.
  • Received Critical Talent Retention Grant from Intel CEO Pat Gelsinger

Timeline

SoC Validation Engineer

Intel
06.2019 - Current

Driver Development Engineer

Intel
09.2017 - 06.2019

Graduate Technical Intern

Intel
07.2016 - 07.2017

Master of Technology - Computer Science

VTU (BMS College of Engineering)
04.2001 -

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Parvathy GSoC Debug Engineer