Pavan Tejesh Murari
Vijayawada
Summary
Creative and detail-oriented Design Intern considered exceptionally quick learner. Effective team player with strong time management skills to complete projects on time and under budget.
Overview
1
1
year of professional experience
Work History
Analog Layout Design Trainee
Sumedha IT
Hyderabad
07.2024 - Current
- Created schematic diagrams and layout drawings for standard cells, such as NAND, NOR, and inverter. Verified DRC and LVS. Implemented inverter routing in different metal tracks.
Associate Trainee Engineer
KPIT Technologies
Bengaluru
12.2023 - 08.2024
- Conducted research into new technologies, applications, protocols, and products.
- Performed system design tasks such as coding, debugging, testing, and documentation.
Education
B.Tech - Electronics And Communications Engineering
VIT-AP University
Amaravati, Andhra Pradesh08-2024
High School Diploma -
Sarada Junior College
Vijayawada, India05-2020
Skills
- Good Kowledge on CMOS Fundamentals
- Good Knowledge on LVS and DRC
- Layout Design of various standard cells
- Good Knowledge on scripting languages ie TCSH
Layout Tools
Technology: TSMC 28nm.
Layout Tool: cadence virtuoso Layout XL.
Schematic Tools: cadence virtuoso schematic XL
Verification Tools: Mentor Graphics Calibre.
Operating system: LINUX
Affiliations
- Lead at CSI VITAP Chapter.
- Finalist at HACKAP Hackathon.
Projects
- Made a Project on IOT BASED HEALTH CARE MONITORING SYSTEM as a part of a course.
- Developed a surveillance robot which can be controlled by a web server.
Languages
Telugu
First Language
English
Proficient (C2)
C2
Timeline
Analog Layout Design Trainee
Sumedha IT
07.2024 - Current
Associate Trainee Engineer
KPIT Technologies
12.2023 - 08.2024
B.Tech - Electronics And Communications Engineering
VIT-AP University
High School Diploma -
Sarada Junior College
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