Premalatha Chilakala

An enthusiastic & high energy determined professional seeking senior level assignments in physical design with a reputed organization where my skills and abilities can be used to achieve company’s goals and thereby mutual growth.

SUMMARY Of EXPERTISE:

12+ years of experience as a Physical Design Implementation Engineer, involving in ~16 successful tape outs of flat and hierarchical chips, complete ownership of implementation and closure of complex blocks of frequencies 2GHZ,1.2 GHZ, 1.4 GHZ, 1GHZ,800Mhz etc. having gate count from 800K to 3.2 million.

Worked in aspects of Synthesis/PD/STA/PV and power signoff requirements. Gained good experience through successful tape outs in 5nm,7nm,14nm, 12nm and 10nm.

Worked on design complexity ranging from 600k to 3.2M Gate count. Responsible for Partition closure which includes, Floor planning, Power plan, Placement, CTS, Routing, & STA, Extraction, DRC, LVS. Routability analysis & post-route optimization, and addressing routing DRC, LVS. Fixing post-route timing closure with STA by using primetime and fixing crosstalk.

Worked on MV designs, good Knowledge in UPF, and low power methodologies. Worked on ECO iterations to reach timing closure by interacting with front-end designers. Knowledge of IR/EM checks on design and solved the design issue with respect to IR and EM.

Debugged the failures which cause non-equivalence between golden and revised netlists and fixed the issues after analyzing the schematics.

Effectively worked with all the individual block designers to fix their respective ends of the timing Paths and made recommendations on various types of fixes.

• Performed chip level integration, block and section level timing closure and chip level cross talk, noise analysis.
• Handled high congested designs, High frequency timing paths.
• Effectively working with all the individual block designers to fix their respective ends by Performing multiple iterations of floorplan with proper analysis of data-path and bus communications for the effective usage of core area to achieve less congestion, best routability and timing results.
• In routing address routing-DRC with route-guides being created, more shorts and RV issues due to congestion resolved.
• Responsible for closure of timing critical blocks in multiple projects.
• Working parallel with the team at eco stage, which includes developing and rolling the Eco’s for block level convergence.
• Delivering the database on time, especially at eco stage meet the timelines.

• English
• Telugu
• Kannada

• Received multiple recognition awards from managers for different project execution.
• Got appreciation awards from various cross functional teams.

I, Premalatha hereby declare that the above written particulars are true to best of my knowledge.