PRIYA TRIPATHI

Key Skills: Advanced Node Yield Analysis (FinFET, FD-SOI) · Defect Reduction · Electrical Characterization · SPC/DOE · RCA

• Advanced Node Expertise: Optimized yield for 14nm FinFET, 22FDX, and 12LPP technologies on 300nm wafers by correlating inline defectivity with electrical test failures, improving yield and reducing parametric outliers.
• Root Cause Analysis & Predictive Modeling: Leveraged statistical tools (JMP, GF in-house system) to isolate yield detractors, preventing defect recurrence through targeted process adjustments.
• MACRO Structure Qualification: Led electrical characterization-based qualification of inline inspection macros for a key customer, reducing scrap rate and enabling faster lot release.
• Process Integration & Audit Support: Collaborated with PI/YE teams to qualify for 2024-2025 Internal Audit, standardizing control plans to achieve zero non-conformities.
• Device Performance Optimization: Characterized CMOS, BJT, SRAM, and Ring Oscillators to identify process-sensitive parameters, improving device stability.
• Real-Time Disposition & KPI Improvement: Streamlined lot hold/release decisions using real-time ET-inline data fusion.
• Cost-Saving Process Changes: Evaluated FEOL/BEOL module changes through statistical risk assessments, enabling cost savings via defect reduction.
• Cross-Site Collaboration: Anchored remote FAB operations daily support (Leading Bangalore team)

Contributed to advanced research on quantum well transistors as part of DRDO’s quantum technology initiative. Assisted in TCAD simulations (Sentaurus) to analyze carrier behavior in III-V heterostructures and supported the team in evaluating low-power transistor designs for defense applications.