PRIYANK VIKRAM SINGH
Noida
Summary
Accomplished Staff Engineer at Synopsys India Pvt Ltd with over 8+ years of experience, specializing in custom compiler and layout design. Expert in optimizing PPA analysis and streamlining verification processes through automation. Proven leadership in enhancing project outcomes and delivering high-quality standard cell libraries, demonstrating strong technical acumen and effective collaboration skills.
Overview
8
8
years of professional experience
Work History
Staff Engineer
Synopsys India Pvt Ltd
Noida
05.2025 - Current
- Led planning, scheduling, and execution of custom PVT, achieving superior project outcomes and enhancing deliverable quality.
- Collaborated with global teams to deliver high-quality standard cell IP, ensuring on-time delivery of test chips.
- Designed flip-flops, latches, and complex circuits to satisfy timing and robustness criteria.
- Developed standard cell circuits and layouts from 55nm to 2nm using finFET and GAA technologies.
- Executed physical verification flows, assuring sign-off quality through DRC, LVS, ERC, and reliability evaluations.
- Optimized PPA analysis to meet targets for high-performance standard cells.
- Streamlined verification processes with Python and TCL automation, reducing turnaround time and increasing efficiency.
- Development of Layouts for Standard cell Libraries (High-performance libraries, high density libraries, ultra-high density UHD libraries) meeting aggressive performance, power and area PPA targets under dense design constraints.
- Developed Libraries in cutting edge latest tech nodes like Samsung 2nm, Rapidus 2nm, Global Foundries 55nm BCD, Intel 14AE (with back side power delivery network).
- Designed and optimized Libraries at 2nm-4nm, addressing EUV-driven DRC, pin accessibility, EM/IR, and achieving 10-20% delay improvement and 5-10% area reduction using Synopsys custom compiler tool, IC compiler tool, ICV tool and mentor calibre for signoff checks (DRC, LVS, DFM, ERC)
- Conducted Quality reviews of the cells giving area and metal reduction comments in 5-10% of the cells
- Automated Layout release and QA flows using Bash/TCL, reducing significant manual effort and improving release consistency and quality across teams.
- Developed a Custom compiler cellchk panel to check the status of all checks concurrently while developing and while reviewing the layouts using TCL.
Technical Leader
STMicroelectronics
Greater Noida
03.2022 - 05.2025
- Executed full flow development from backend design to frontend characterization, ensuring design integrity for 130nm technology.
- Implemented new approach for place and route library development in 18nm technology, improving workflow efficiency.
- Developed multibit flip-flop library to minimize area at the SoC level.
- Conducted power performance and area analyses for multibit flip-flop cells in 18nm technology.
- Completed layout and schematic development for various libraries in 18nm and 28nm technologies.
- Transitioned BCD 9T library from 12T library in BCD technology (180nm).
- Developed three-stage synchronizer flip-flops in M40nm technology, calculating tau and MTBF values.
- Managed ticket handling for standard cell team across multiple technologies, streamlining communication and response time.
Memory and Standard Cell Layout Engineer
Zia Semiconductor Pvt Ltd
Greater Noida
06.2018 - 03.2022
- Led layout development for major and minor projects across 40nm, 28nm, and 90nm technology nodes.
- Managed backend library development and integration for 40nm memory compilers, streamlining workflow.
- Conducted schematic and layout development with physical verification for combinational and sequential cells.
- Developed layouts and performed physical verification for high-speed flops and in-situ monitoring flops.
- Validated and packaged MBFF and high-speed cells using UBE flow, ensuring compliance with internal standards.
- Executed evalring and evalflip runs for power performance area validation under various load conditions.
- Reviewed team members' cell designs for quality assurance and compliance with specifications.
- Performed design rule check and layout versus schematic verification on all compilers using UGNGUI.
Education
Bachelor of Technology - Electrical and Electronics Engineering
J.S.S Academy of Technical Education
Gautam Buddha Nagar06-2018
XII -
Emmanuel Mission School
Kota04-2014
X -
Hind Zinc School
Chittorgarh04-2012
Skills
- Custom Compiler
- ICC2
- Cadence Virtuoso Layout
- Calibre
- ICV
- Eldo
- Hspice
- PrimeSim
- Kronos
- Shell scripting
- TCL scripting
- SKILL
- Weblib
- ADOC
- Crossfire
- XA
Timeline
Staff Engineer
Synopsys India Pvt Ltd
05.2025 - Current
Technical Leader
STMicroelectronics
03.2022 - 05.2025
Memory and Standard Cell Layout Engineer
Zia Semiconductor Pvt Ltd
06.2018 - 03.2022
Bachelor of Technology - Electrical and Electronics Engineering
J.S.S Academy of Technical Education
XII -
Emmanuel Mission School
X -
Hind Zinc School