Pushpavathi Vippala
Hyderabad
Summary
Verification Engineer with 5 years of hands-on experience in SOC and IP-level functional verification for Clients including Intel, Texas Instruments, Samsung, and NXP. Proven expertise in UVM-based testbench development, functional coverage closure, and debug across diverse protocols (CXL, AXI, SPI). Experienced across the full verification lifecycle—from test plan creation through regression management and sign-off. Returning to the field with refreshed skills in UVM, SVA
Overview
9
9
years of professional experience
Work History
Ethernet MAC Verification
VLSI Guru
01.2026 - Current
- Executed protocol-level verification of Ethernet MAC layer using UVM and SystemVerilog.
- Conducted TX/RX path verification, implemented error injection scenarios, and achieved functional coverage for frame types, sizes, and back-to-back transfers, enhancing test robustness.
Career Break
11.2022 - Current
- Took a deliberate career break to manage significant personal family circumstances.
- During this period, actively maintained and deepened technical expertise through structured self-study:
- UVM architecture driver, monitor, scoreboard, TLM ports, sequences
- AXI protocol verification all 5 channels, VALID/READY handshake, burst types (FIXED/INCR/WRAP)
- System Verilog OOP concepts, advanced constraints, SVA assertions, DPI, functional coverage.
Senior Verification Engineer
Tessolve Semiconductors
02.2022 - 11.2022
- Performed in-depth analysis of multiple SOC test modes to accelerate SOC debug cycles.
- Built tests for Boundary Scan scenarios.
- Implemented the Test plans for the modules EPW, ECAP where I understood the module application point of view and given presentation on the same with designers.
- Client: Texas Instruments
Verification Engineer
BITSILICA Private Ltd.
02.2021 - 01.2022
- Gained deep understanding of CXL 1.x cache-coherent interconnect protocol, enabling accurate development of error-scenario test cases at the cluster level.
- Verified error-handling functionality within the CXL cluster, validating protocol compliance for cache coherency between CPU memory and attached accelerators.
- Analyzed existing test infrastructure and enhanced test coverage for targeted error scenarios, contributing to protocol sign-off readiness.
- Client: Intel
Verification Engineer
BITSILICA Private Ltd.
08.2020 - 02.2021
- Executed functional verification of the POSTCE block within a 5G NR modem SOC, ensuring correctness of receiver-to-transmitter communication paths.
- Managed and triaged regression suites for the modem engine, identifying failures and escalating RTL bugs for timely resolution.
- Client: Samsung
Verification Engineer
BITSILICA Private Ltd.
01.2020 - 08.2020
- Authored the full verification plan for the SPI controller, covering master/slave full-duplex communication, interrupt handling, and DMA transfer scenarios.
- Developed constrained-random UVM test sequences for interrupt and DMA transfer verification, achieving comprehensive functional coverage across operating modes.
- Implemented a functional coverage model tracking SPI transfer modes, word lengths, and clock polarities, driving coverage closure to sign-off targets.
- Client: In-house
Verification Engineer
Wipro Technologies
08.2018 - 01.2020
- Implemented the verification test plan for DMA (MENG) instruction set at unit core level, covering instruction encoding, execution, and exception handling.
- Built self-checking subroutines in Perl for automated validation of processor instructions, reducing manual verification effort and improving regression reliability.
- Developed directed test cases and assertion-based checks for critical processor signals, achieving measurable improvement in assertion coverage metrics.
- Analyzed coverage reports to 100% and devised new stimulus scenarios to close functional coverage gaps, directly contributing to product sign-off.
- Client: Intel
Verification Engineer
Wipro Technologies
04.2017 - 07.2018
- Verified SERVICE_PROCESSOR (Cortex-A5) and SECURE_FUSE_PROCESSOR modules at SOC level, validating multicore handshaking and secure boot flows.
- Authored C-based directed test cases for multicore handshaking scenarios, ensuring correct inter-processor communication on a SoC.
- Debugged RTL code and filed detailed bug reports; verified RTL fixes and confirmed test results to ensure defect closure before tape-out.
- Generated and analyzed functional coverage reports, identifying under-covered scenarios and driving regression runs to meet coverage targets.
- Client: NXP Semiconductors
Education
PG Diploma - VLSI Design
Maven Silicon
01-2017
B.Tech - Electronics & Communication Engineering
Vignana Bharathi Institute of Technology (JNTUH)
01-2016
Skills
- System Verilog
- UVM (Universal Verification Methodology)
- Constrained-Random
- Coverage-Driven
- AMBA-AXI
- SPI
- CXL
Accomplishments
Awarded 'Inspiring Performer' recognition at Wipro for outstanding contributions to the Intel PUMA Processor verification.
Timeline
Ethernet MAC Verification
VLSI Guru
01.2026 - Current
Career Break
11.2022 - Current
Senior Verification Engineer
Tessolve Semiconductors
02.2022 - 11.2022
Verification Engineer
BITSILICA Private Ltd.
02.2021 - 01.2022
Verification Engineer
BITSILICA Private Ltd.
08.2020 - 02.2021
Verification Engineer
BITSILICA Private Ltd.
01.2020 - 08.2020
Verification Engineer
Wipro Technologies
08.2018 - 01.2020
Verification Engineer
Wipro Technologies
04.2017 - 07.2018
PG Diploma - VLSI Design
Maven Silicon
B.Tech - Electronics & Communication Engineering
Vignana Bharathi Institute of Technology (JNTUH)