Raghupathruni Yeswanth Harinivas

To secure a challenging position as a Senior DFT (Design for Test) Engineer, leveraging over 5 years and 9 months of experience in the field. Adept at leading and managing teams, my expertise includes proficient handling of MBIST (Memory Built-In Self-Test), Scan, Compression, ATPG (Automatic Test Pattern Generation), Simulations, LEC (Logic Equivalence Checking), and Post Silicon bring up and validation. I am committed to delivering high-quality test solutions, optimizing test coverage, and ensuring seamless post-silicon validation for complex semiconductor designs.

• AMD-XILINX, Developed a sophisticated counter system to accurately calculate on-chip clock frequencies in silicon., Implemented a robust solution that provides precise measurements, contributing to efficient clock management and optimization. Significantly reduced the complexity by employing a minimalist logic design approach while ensuring high accuracy in frequency calculations.

• Unix
• Perl
• Tcl

• Named Capture Procedure (NCP) Generation
• Smart Scan Pattern Conversion
• Flow Retrieval Automation
• Pattern File Splitting
• Bench Debug Flow Generation and APB and PCSR Registers Programming

• Tessent for comprehensive DFT (Design for Test) solutions.
• Formality and Conformal for Logic Equivalence Checking (LEC).
• VCS and Incisive for timing and notiming simulation purposes.
• Competent in using Vivado for FPGA synthesis, implementation, and verification.