Rahesh R
Chennai
Summary
Accomplished Physical Design Engineer with expertise in low-power design and timing optimization, achieving a remarkable 90% reduction in runtime through enhanced floorplan flow. Proven ability to streamline processes via scripting for greater efficiency. Recognized for strong coordination skills in handling complex projects, delivering timely, and innovative solutions in high-pressure environments.
Overview
3
3
years of professional experience
Work History
Physical Design Engineer
Qualcomm
Chennai
07.2022 - Current
- Managed a complex block with over a million instances, 100+ memories, multiple clocks (up to 320 MHz), and multiple power domains, and a complex shape with numerous edges.
- Developed a custom method to reduce always-on buffering for 7,000 feedthroughs. Handled numerous functional ECOs without affecting timing.
- Led a test chip project with over a million instances, 90+ memories operating at a 384 MHz clock, and a 1.9 GHz clock shared with IPs.
- Managed partitioning, floorplan, and PNR within a tight 5-month timeline, coordinating with package and IP teams for smooth completion.
- Implemented functional ECOs, requiring the addition of macros in the PNR stage for product tapeout.
- Worked on a subsystem with over a million instances, multiple clocks, and power domains. Successfully implemented a new switching method, and developed efficient scripts for reuse partitioning.
- Enhanced the floorplan flow for better PV and PDN closure in a 6nm project, saving 90% of runtime during the ECO phase.
- Supported in multiple projects for timing and PV closure, addressing critical issues in highly congested regions.
ICE Physical Design Engineer
Intel
Bangalore
04.2022 - 06.2022
- Worked on layout verification areas such as LVS, DRC, and antenna checks, on the 5nm project.
Education
Advanced Diploma - Physical Design
RV VLSI
02.2022
Bachelor of Engineering - Electronics and Communication Engineering
PSG Institute of Technology And Applied Research
04.2021
Skills
- Low power design
- Physical verification
- Static timing analysis
- Scripting and automation
- EDA tool proficiency
Accomplishments
- Got Spotlight award for excellent work in enhancing the CAD flow in a 6nm project.
Languages
Tamil
First Language
English
Upper Intermediate (B2)
B2
Timeline
Physical Design Engineer
Qualcomm
07.2022 - Current
ICE Physical Design Engineer
Intel
04.2022 - 06.2022
Advanced Diploma - Physical Design
RV VLSI
Bachelor of Engineering - Electronics and Communication Engineering
PSG Institute of Technology And Applied Research
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