RAHUL VISHAL

Working as Director - ASIC Design at Alphawave Semi , talented with excellent employee development, customer service and analytics skills coupled with more than 23 years of experience. Comfortable giving engaging presentations to clients to drive new business, expand accounts and establish brand profile. Excellent team builder and leader of initiatives. Passionate about applying excellent organization and communication skills to manage and lead teams.

In Past, worked as SOC Design Engineering Manager at Intel India prior to Alphawave. Adept in complete closure of Physical Design (from RTL to GDS2) with added expertise in large Team Management. Expertise in driving complex projects to completion, managing large teams, and achieving SOC convergence. Skilled in PD, STA, DFT, DRC, Signal EM, IR analysis, etc and fostering a goal-oriented team environment, demonstrating exceptional leadership and technical prowess.

Encouraging manager and analytical problem-solver with talents for team building, leading and motivating, as well as excellent customer relations aptitude and relationship-building skills. Proficient in using independent decision-making skills and sound judgment to positively impact company success. Dedicated to applying training, monitoring and morale-building abilities to enhance employee engagement and boost performance.

Pursuing full-time role that presents professional challenges and leverages interpersonal skills, effective time management, and problem-solving expertise.

Director - ASIC Design (Alphawave Semi)

• Ridley aka Switch : Managing a team of 60+ people to deliver the complete SOC to client (Major networking company based out of US) with NextGen Switch.

Physical Design Manager (Intel Semiconductors)

• GNRD-IO Die - Managed a team of 60+ employees (internal and contract workers) to deliver the various milestones for 2 SubFCs (Tiles) and 1 SS in Physical Design. Horizontally, owning the FCT & Power convergence team.

SOC FCT Execution Lead and Manager (~2 years)

PVC Base Die SOC FCT - Managing Team of 35+ people towards the single goal of SOC FCT convergence. This also includes the noise and caliber (intel internal ruleset for quality)

Design Complexity

• 64M Instances – Flat SOC FCT Model using PrimeTime
• 2.4K Clocks – Highest Clock Freq 2.4Ghz
• 650mm2 10nm Base Die
• Intel 10nm Process

ATS SOC FCT - Managing Team of 25+ People towards the single goal of SOC FCT convergence. This also includes Noise and Caliber (intel internal ruleset for quality)

Design Complexity

• 45M instances – Flat SOC Model using PrimeTime
• 1.4K clocks – Highest Clock Freq 2Ghz
• Intel 10nm Process

SOC Timing Lead for: (~5 years)

Broadwell Chops - DE, LCC, MCC, HCC

• Broadwell is the fifth model generation of Intel Processor. It's Intel's codename for the 14 nanometer die shrink of its Haswell microarchitecture. It is a "tick" in Intel's tick–tock principle as the next step in semiconductor fabrication. Like some of the previous tick-tock iterations, Broadwell did not completely replace the full range of CPUs from the previous microarchitecture (Haswell), as there were no low-end desktop CPUs based on Broadwell

BDXNS-CPM

• BDX-NS is an SoC derivative of Broadwell Server-DE (Xeon D), a Xeon class server SoC product targeted for Network & Storage markets. The key changes in this Xeon SoC derivative with respect to the baseline product are the integration of Crypto Processing Module (CPM) IP on die to provide Intel QuickAssist capability, the addition of two new 10 GBASE Kerem ports (KR) and associated Media Access Controllers (MAC) to support these KR ports. In short, we had to integrate two silicon proven IPs into a PRQ’ed SoC

Member of POSH team @ Alphawave Semi

• Investigated a case of harrasment as a POSH member

Reviewer @ Intel:

• DTTC Reviewer for 2021, 2017 & 2019 (Design Test and Technology Conference)
• Approved Timing Reviewer for SDG 10nm
• Reviewed multiple projects for various milestones – like ICXD, SPR IPS, ICXSP – IPS, etc

Mentor @ Intel:

• Recognized Mentor for GTCHE – Virtual Speed Mentoring Program
• Recognized as a Mentor for XNE D&I (Diversity and Inclusion)

Coach @ Intel:

• Training Class given at Intel Learning Platform - Timing Basics and STA Overview (ID: 20005313)

Educational Summary

I have done my ME in Microelectronics from BITS, Pilani in 2000-2001 with CGPA 9.51, and my BE in Electronics and Communication from MVJ College of Engineering, Bangalore in 1995-1999, with a 4 years aggregate of 72.5%.