Summary
Overview
Work History
Education
Skills
Hobbies: -
Declaration:
PersonalDetails:
PROJECTS:
Experience Summary:
TRAINING:
Timeline
Generic

RAJU K KUNTALA

Telangana

Summary

  • To work as successful Physical Design engineer in a challenging and dynamic environment and to add values to the Organization I serve, while concurrently upgrading my skills and knowledge.

  • Expertise in Physical design concepts with entry-level exposure to using EDA tools, flows &methodologies.
  • Experience in Place and route, Timing closure, DRC/LVS of partitions/blocks in28nm technology node.
  • Expertise in Static Timing Analysis (STA).
  • Concepts Netlist to GDSII Implementation
  • Synthesis, Floor-planning, power planning, Place and route, Clock tree synthesis, Routing and Optimization using Synopsys Tool (ICC2).
  • Signoff-Timing, DRC
  • In CTS clock signal is distributed to all the sequential cell pins in the design by maintaining minimum clock skew and minimum clock latency and performing clock routing of all standard cell pins and macro pins.
  • Analyzing timing reports for setup and hold violations and reducing timing violations by using different methods like (upsizing, VT swapping, buffer insertions, etc.)
  • And Timing analysis on different path groups for registers, having multiple clocks, data path, and clock path.
  • Routing of all standard cell pins and macro pins using metal layers, performing via optimization and post-route optimization by considering signal integrity effects on timing.
  • Adding Routing blockages between macros to macros and macros to the core boundary for reducing the Routing Congestions.
  • Hands-on Experience in Synopsys IC Compiler II tool and Primetime tool.
  • Implemented block level multi voltage Floorplan Design meeting the power and timing requirements. Capable of resolving placement, CTS, and routing stage. Timing, constraints, and congestion issues.
  • Clock Tree Synthesis implementation and optimization. Handled detail routing including LVS, DRC, and Antenna violation fixes.

Overview

10
10
years of professional experience

Work History

Technical Lead

HCL Technologies
05.2024 - Current
  • Worked on semiconductor ion implanter platforms including Trident XP, Trident XP2, and Athion for wafer manufacturing equipment.
  • Designed electrical schematics from scratch for Washington and Semco Platen Heater Controllers.
  • Selected and validated electrical components including wires, cables, connectors, terminals, relays, contactors, circuit breakers, rectifiers, RTD sensors, line filters, and power distribution components.
  • Developed 3D models, cable routing, harness flattening, and naiboard drawings using CAD tools for controller assemblies and system racks.
  • Designed and modified electrical assemblies within Tool Control Rack, Electronics Rack, and controller subsystems.
  • Worked on critical Athion subsystems including AE HV Modulator, EPM Dose Controller, Dose Controller, Dose Digitizer, Backside Gas Cooling Controller, ESC Extraction Power Supplies, Capacitor Switch, ISO Grid Transformer, UPS Isolation Transformer, E-Media Converters, Leak Sensors, GND I/O, and HV I/O Assemblies.
  • Prepared and implemented Engineering Change Orders (ECOs), generated ECO PDFs, and managed engineering change documentation.
  • Performed ECO sign-off and release activities using Agile PLM.
  • Retrieved and verified Bills of Materials (BOMs) from SAP and compared them with Windchill BOMs to ensure design and manufacturing consistency.
  • Collaborated with cross-functional teams including electrical, mechanical, manufacturing, and quality engineering to support product development and engineering changes.
  • Supported product development from concept through release while ensuring compliance with engineering standards and manufacturing requirements.
  • Project: Washington platen heater controller
  • Client: Applied Materials

Senior Engineer

L& T Technologies
08.2022 - 05.2024
  • WorkingonSchematiccorrections forControl Panel Harnesses
  • WorkedonHarnessdesigncorrections forDiesel main, Gas main, Telematics, CDVR CB harnesses, current sensing, voltage sensing, parallelling concept harnesses.
  • WorkedonComponent,CircuitBreakerterminalandconnector,wireandcableselections.
  • WorkedonHarnessdesignfor Diesel main, Gas main, Telematics, CDVR CB harnesses.
  • Worked on BG Drawings & GMJT's, worked on production build issues
  • Project: ECS (Energy Control System)
  • Client: Caterpillar

Senior Engineer

ARI-AutomotiveRoboticsIndiaPvtLtd.
07.2021 - 08.2022

  • Project:NGC(next generation Controls)
  • Client:Caterpillar (Onsite)

Engineer III

ARI-AutomotiveRoboticsIndiaPvtLtd.
12.2020 - 08.2022
  • Design and develop conceptsforNewProduct Introduction, ContinuousProduct Improvement, Field failure issues.
  • DesignedHarnessroutingsforC32DesigntoOrderProjects,aspercustomerrequirement.
  • HarnessAutopackagingusingElectricallines.
  • SelectionofHardwareforMountingofcablesandHarnesswithoutinterference.
  • WorkedonBackgroundWiringGP drawings.
  • Project:C32DTOPProject
  • Client: Caterpillar

Design Engineer

Axiscades Engineering &TechnologiesLtd.
09.2017 - 12.2020
  • A. Designed Harness Assemblies and Wiring Groups for C280 Marine Engine
  • Validating C280 12 Cylinder, 16 Cylinder harnesses as per schematics and changed all wires to LSHF to comply with IEC standards for Marine application.
  • Designed and Detailed common rail harness wiring for 6, 12 Cylinder& 8, 16 Cylinder engines for C280 model.
  • Created GMJT's for C280 Engine for different cylinders, worked on BG Drawings
  • B. Commonising Project (C280 Marine Engine)
  • For Cost Reduction and for ease of assembly and service created Variable Geometry Harness assemblies using Parent Assemblies on 8,12 cylinders which are Compatible with 12, 16 Cylinders respectively.
  • Responsible for design updates, design verification of all Wiring, Harness Groups and release as per CAT standards.
  • Designed common rail harness wiring in schematic for 6,12Cylinder& 8,16 Cylinder engines for C280 model.
  • C. VDRA Issues and ECR
  • Interacting with CAT Engineer and resolved ECRs and CI CARDS for different Engines.
  • Created GMJTs and cleared various VDRA issues.
  • Proficient in handling Database management systems like EDS and TEAMCENTRE.
  • Exhibited Delivery excellence by providing Customer Projects within time.
  • Project:C280 Marine Engine
  • Client:Caterpillar
  • Project:C280 Marine Engine
  • Client:Caterpillar

05.2016 - 09.2017
  • 1.3 yrs worked as a electrician for Golden star facilities pvt ltd.
  • Provided good support to maintain in LT panels in the floor, circuit brakers, fire safety.
  • Checking the conditions of UPS 's, AHU

Education

M. Tech -

S.P.R College of engineering & Technology
Hyderabad
01-2017

B. Tech -

Jyothismathi college of engineering &technology
Karimnagar
01-2014

Intermediate -

Narayana Jr. college
AP
01-2010

SSC -

Z.P.H School
Endapalli
01-2008

Skills

  • CREO parametric 30, 40, 750, 120
  • CREO SCHEMATICS 30
  • ProE Diagram
  • Windchill
  • Agile
  • SAP
  • TEAMCENTER Visualization Mockup 101, 112, 11
  • PLM Teamcenter
  • Linux/Unix Commands, tcsh /tcl Shell scripting, Floor planning, Power analysis, Placement, CTS, STA, Routing, Signal Integrity, Antenna Effect
  • Good communication and presentation skills
  • Ability to rapidly build relationships and trust
  • Confident and determined
  • Ability to cope with different situations
  • Good decision-making and better time management
  • Time management
  • Smart working

Hobbies: -

Playing cricket, Listening to spiritual messages and songs, Counseling / Motivating youngsters., Reading books

Declaration:

I herebydeclarethattheabovewrittenparticularsaretruetothebestof myknowledgeandbelief and can be supported with reliable documents whenneeded. Date: Place:Hyderabad (Raju K)

PersonalDetails:

Languagesknown : English,Hindi,Telugu

PROJECTS:

  • A. 32Bit RISC Processor [ORCATOP], Technology/Layers :28nm/9Metal layers, Tool used :Synopsys IC, Macros :40, STD cells :52K, No. of clocks :8, Clock Frequency : 450MHz, Utilization :70%, Implemented RISC Core Processor multi-voltageblockleveldesignnon28nmTechnology Node., Acquired knowledge in Physical Design Flow involving Floor-planning, Macro placement, Power analysis, standard cell placement, clock tree synthesis (CTS), STA, and Routing., Understanding the concepts of core area and die area, to get less congestion throughout the design., Worked on the floor planning and macro placing to get a compact but good design with no DRC error with less Congestion ensuring good routebility., Placing the macros manually using the set of guide lines and flyline analysis., Understanding the Power script for multi-voltage design and power ring creation around the macros with no DRC, Missing vias, and floating wires errors., In placement all the standard cells are pulled in to the core region and performed HFNS followed by placement legalization with incremental optimizations making the design congestion-free.
  • M. Tech Project:, Title: Power quality improvement using interlined power quality conditioner, B.Tech Project:, Title:LCL VSC Converter for high voltage applications, Team Size: 4

Experience Summary:

  • 9 years in Design, Detail and Product Development
  • Expertise in creating a new schematic design and functionality from scratches along with Modeling, flattening and detailing of Harness.
  • Wide knowledge of Electrical components selection, cable harness assembly and Wiring group designs.
  • Expert in using Electrical Lines for Routing of cables in Creo.
  • Electrical Wiring Harness and cable routing, selection of spools based on wire gauge, design of electrical components connector, terminals P-clamps etc.
  • Well Experienced in Harness design for large assemblies with auto packing of wires along with flattening and detailing.
  • Experienced in Harness drawing creation and checking.
  • Creation of JT and GMJT files by Creo and Team center Vis mockup.
  • Working with Product lifecycle management (PLM) Team center, Team center Vis mockup, Rocket Blue zone, BNU and HVC
  • Creating change notice process for drawings to move forward(Checking and Releasing) the project as per CAT standards
  • Decision making in Validating and reviewing in design level.
  • Basic knowledge in GD&T and applying them in various levels
  • Good knowledge in Team center change packages and workflow process, BNU creation, Black Screen, Uploading and Downloading files from TCE.
  • Taking complete ownership for a design or project, handling high priority projects, and providing satisfactory design.
  • Gaininganinsightintotheproduct,withtheaimofcontributingeffectivelytotheprjject.

TRAINING:

  • VLSIGURU Training Institute
  • Aug2024–Dec2025

Timeline

Technical Lead

HCL Technologies
05.2024 - Current

Senior Engineer

L& T Technologies
08.2022 - 05.2024

Senior Engineer

ARI-AutomotiveRoboticsIndiaPvtLtd.
07.2021 - 08.2022

Engineer III

ARI-AutomotiveRoboticsIndiaPvtLtd.
12.2020 - 08.2022

Design Engineer

Axiscades Engineering &TechnologiesLtd.
09.2017 - 12.2020

05.2016 - 09.2017

M. Tech -

S.P.R College of engineering & Technology

B. Tech -

Jyothismathi college of engineering &technology

Intermediate -

Narayana Jr. college

SSC -

Z.P.H School
RAJU K KUNTALA