RAKESH REDDY
Hyderabad
Summary
Dynamic Power Engineer with hands-on experience in power estimation and optimization, developed through impactful work at SiFive. Skilled in leveraging industry-leading tools such as Cadence Joules, Ansys PowerArtist for RTL power analysis, and Synopsys PrimeTime PX (PTPX) for gate-level power Analysis. Demonstrated success in implementing power reduction strategies to improve system efficiency. Adept in Cshell and TCL scripting, with a strong track record of cross-functional collaboration, and delivering results in high-performance embedded systems.
Overview
4
4
years of professional experience
1
1
Certification
Work History
Power Engineer
SiFive
Bengaluru
10.2024 - Current
- Engineered embedded RISC-V IP Cores utilizing 3nm, 5nm, and 16nm technology nodes.
- Implementing architectural & micro-architectural optimizations, including: Clock-gating, Data-gating.
- Collaborated with Power DV team to design rigorous test cases for CPU IPs, featuring Dhrystone, Max Power, SGEMM, and bandwidth tests for memory access ports along with multiple ML tests like softmax.
- Worked on technology scaling from 5nm -> 16ff & 16ff -> 28hpc , analyzing its impact on power, area, and performance.
- Evaluated power and area trade-offs, optimizing designs for efficiency and scalability.
- Focused on power estimation, optimization, and budgeting to enhance efficiency.
- Performed power analysis and optimization using industry-standard tools, including Ansys PowerArtist for RTL-level power estimation and reduction, and Synopsys PrimeTime PX (PTPX) for gate-level power analysis.
- Driving power reduction strategies to improve overall performance and Power efficiency.
Product Validation Engineer
Cadence Design Systems
Noida
02.2021 - 09.2024
- Worked on EDA tools: Joules RTL Power Solution, Joules RTL Design Studio, Genus Synthesis, and Innovus.
- Feature Testing (Joules RTL Power): Validated features like Xreplay, CGLAR, Power Computation, etc.
- Power Reduction Technologies: Tested ODC, STB, Data Gating, and other optimization techniques.
- Regression Infrastructure Development: Designed and automated code check-in, build creation, regressions, failure assignment, and reporting from scratch.
- Benchmarking & Build Qualification: Established benchmarking runs and qualified builds weekly for Joules RTL Power & Joules RTL Design.
Education
Bachelor of Science - Electronics & Communications
Manipal University Jaipur
Jaipur,India08-2020
Skills
- Power estimation and optimization
- Power analysis tools
- Cadence Joules calculator
- Ansys Power Artist
- Synopsys PTPX
- Cshell and TCL scripting
- Linux operating system
Certification
- Gained hands-on experience with digital circuit design and foundational Verilog programming
- Learned key concepts in SystemVerilog for RTL design and verification
- Developed a strong understanding of digital logic and verification workflows
Languages
Telugu
First Language
English
Advanced (C1)
C1
Hindi
Proficient (C2)
C2
Timeline
Power Engineer
SiFive
10.2024 - Current
Product Validation Engineer
Cadence Design Systems
02.2021 - 09.2024
Bachelor of Science - Electronics & Communications
Manipal University Jaipur
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