Ronodeep Gupta
ASIC Design Engineer - I (DFT)
Bengaluru
Summary
ASIC Design Engineer with almost 2.5 years experience in ASIC design implementation and verification. Worked as part of dynamic design team employing cutting-edge design methodologies to support next-generation ASIC products.
Overview
2
2
years of professional experience
Work History
ASIC Design Engineer
Alphawave Semi
06.2022 - Current
- Designed SOC Architecture for hierarchical, non-abutted designs based on 40nm and 6nm technology nodes, which included complex security requirements with respect to DFT, multi mode MBIST Repair, Multi Bonding BSCAN and Hierarchical ATPG.
- Designed, implemented and verified DFT for multiples IPs such as PCIE, UFS, DDR, Ethernet, PLL, PVT and Secure OTP.
- Worked on Post-Silicon Debug for IPs such as DDR and UFS, MBIST and MBIST Repair, ATPG.
- Designed and implemented a push-button end to end DFT flow per unique physical partition using TCL and Bash scripting. Held the responsibility for owning and maintaining central DFT automation.
- Debugged variety of simulation failures across all DFT domains both in zero delay and SDF based simulations using Questa and Xcelium.
- Experienced handling TIER 1 customers and representing overall DFT during client-status meetings, resulting into good communication skills.
- Hands-On experience with EDA tools such as Tessent MBIST, Tessent ATPG and Tessent BSCAN, Synopsys SMS MBIST, Genus Synthesis and Tempus Timing Solutions.
- Collaborated with physical design teams to verify DFT SDC constraints to achieve timing closure and optimize place and route.
Education
Bachelor of Technology - Electrical, Electronics And Communications Engineering
Meghnad Saha Institute of Technology
Kolkata, India 04.2001 -
High School Diploma -
MP Birla Foundation HS School
Kolkata, India 04.2001 -
Skills
MBIST and MBIST Repair
BSCAN
ATPG
DFT SDC Constraints
IP DFT
Automation and Scripting
DFT Specification Writing
Communication Skills
Accolades
- Won the Extra Mile Award for designing, implementing and verifying end to end DFT in a test chip based on 40nm for a TIER 1 customer.
- Won the Above and Beyond Award for contribution towards different project's architecture and handling pre-sales customer calls with respect to DFT.
Timeline
ASIC Design Engineer
Alphawave Semi
06.2022 - Current
Bachelor of Technology - Electrical, Electronics And Communications Engineering
Meghnad Saha Institute of Technology
04.2001 -
High School Diploma -
MP Birla Foundation HS School
04.2001 -