Arpit Tiwari

Have good exposure in ATPG coverage analysis and debugging low coverage at tile level (IP level). Worked on simulation timing & zero delay mismatches debug using VCS/Verdi tool at tile level. Worked on Spyglass to identify clock without control, reset & back to back gater issue. Worked on ATPG Trace DRC Analysis & Cleanup for IP level & SOC level. Worked on SOC level to debug translation, merge and readback issue, simulation issue. Worked on prime-time tool to validate setup & hold violation for timing simulation issue at tile level. Worked debug activity on POST silicon failure for Vmin & Vmax issue (shmoo plot). Worked on Scan Insertion & MBIST, IJTAG verification by simulation.

Mentorgraphics Tessent  , Synopsis Design Complier & Fusion Complier , VCS & Verdi