SAI PAVAN KUMAR KANDREGULA

Project 3:

Block: Tile4

Design spec: 2 million Instance count, 44 macros operating at 960 MHz

Tools: Innovus , ICC2

• Owned and handled the block from floorplan to signoff, driving implementation, timing closure, physical verification and ECO activities across all stages.
• The design has 7K Feedthrough ports. Feedthrough buffering was handled using a custom tcl script and port placement was performed accordingly to avoid crisscross connections
• Implemented TI (Transport inverter) as preroutes at the floorplan stage and addressed various challenges related to TI Implementation.
• Added hold padding to avoid hold violations caused by 8T flop Implementation
• Analyzed and addressed timing degradation at different stages of the block, including placement, CTS and post-route.
• Analyzed FV non-equivalents and CLP violations. Fixed PDN high resistance violations, DRV violations such as max transition and max capacitance, along with DRC, LVS and crosstalk fixes.
• Implemented ECO's to achieve signoff quality and addressed block-level timing by consuming tweaker, primeclosure and DMSA eco's.

Project 2:

Block: Tile3

Design spec: 3 million Instance count, 128 macros operating at 960 MHz

Tools: Innovus , ICC2

• Owned end-to-end block-level physical design from floorplan to sign-off (placement, CTS, routing, PDN, STA, PV, FV/CLP), delivering a fully clean block across multi-corner, multi-mode scenarios.
• Transformed a congestion- and timing-critical block by reducing global congestion from 1.29 to 0.13 through congestion-driven placement, block shape optimization, macro re-placement, and partial blockages. Improved setup timing from 800 ps to 50 ps via Vt optimization and floorplan refinement.
• Resolved severe hold violations at CTS stage (-1.2 ns across 12 paths) by applying placement bounds and targeted optimization, achieving near-clean hold closure at -0.04 ns (40 ps).
• Reduced routing shorts significantly from 800 to 65 by optimizing port placement patterns and introducing routing blockages in high-density regions; achieved zero DRC and zero shorts during the ECO cycle.
• Drove sign-off quality timing closure by fixing max transition, max capacitance, crosstalk, antenna violations, and closed timing using Tweaker, DMSA, and PrimeClosure, ensuring robust cross-corner convergence.

• Working as a physical design engineer.
• Handled various aspects of physical design, such as floorplan, clock tree synthesis, and routing.

• Parent company: Terascale Technologies Pvt Ltd

Project 1:

• Responsible for Place & Route, Timing, and PV closure. Resolved congestion issues during macro placement by following macro placement guidelines.
• Handled various sign-off issues while managing blocks such as CLP, UPF, and LEC. Addressed DRV fixes like DRCs, LVS, and antenna during ECO implementation.
• Created PG regions for multi-voltage domain implementation. Performed a customized placement of level shifters.
• Implemented analog routing and custom routes, guiding placement in macro channels with checker-box blockages to enhance design flow.

• Worked on Digital VLSI as a Physical Design Engineer from RTL to GDSII.
• Utilized Cadence (Genus and INNOVUS) and Synopsys (DC, ICC2, and PrimeTime) tools for various design projects.
• Enhanced and automated RTL to GDSII Proteantecs flow to increase efficiency.
• Diagnosed bugs and determined root causes to improve design reliability.