Salman Latif

• Kept project leaders regularly updated with progress, maintaining open, productive communication.
• Collaborated with test design team to enhance test coverage
• Managed verification processes for major projects, encompassing strategy development, planning, execution and final sign-off

• Executed functional verification for PCIe/CXL Power Management block.
• Developed SystemVerilog testbench and assertions for PCIe/CXL Power Management.
• Collaborated with cross-functional teams on diverse PCIe/CXL verification blocks.

Key achievement

• Achieved 15% improvement in functional coverage.
• Identified multiple critical bugs during testing.
• Designed a SystemVerilog testbench for the PCIe controller to enhance verification processes.

• Developed Python scripts to validate Bluetooth Firmware functionalities.
• Simplified verification using a single model for BLE and BR/EDR.
• Gained experience with Bluetooth architecture.