Work Preference
Summary
Overview
Work History
Education
Skills
Languages
Timeline
Hobbies and Interests
Personal Information
Generic
Sanjana Mookim
Open To Work
Verified
This profile is verified using an email address.

Sanjana Mookim

Bengaluru

Work Preference

Job Search Status

Open to work

Desired Job Title

Senior Staff Design Verification EngineerProject LeadFunctional Verification Engineer – Hardware DeveloperASIC Verification EngineerDesign Verification Engineer

Work Type

Full Time

Location Preference

On-SiteRemoteHybrid
Location: Bengaluru, Karnataka
Open to relocation: Yes

Minimum Desired Compensation

₹4300000/yr

Important To Me

Career advancementWork-life balanceCompany CulturePersonal development programs

Summary

Accomplished Design Verification Engineer with 9 years of experience in ASIC/IP level verification and UVM methodology. Expertise in computer architecture and coding in SystemVerilog, C++, and Python. Developed comprehensive test plans and led bug resolution processes, enhancing product quality and driving innovation in complex problem-solving.

Overview

4
4
Languages
1
1
Certification
9
9
years of professional experience

Work History

Senior Technical Lead

Quest Bitsilica Services Private Limited
Bangalore
06.2026 - Current
  • Project - Under NDA
  • Client - Marvell
  • Tasks not yet assigned

Senior Staff Design Verification Engineer

Insemi-Infosys
Bengaluru
10.2025 - 05.2026
  • Project - Under NDA
  • Client - Google
  • Developed and executed register access test cases to validate functionality and performance.
  • Performed root cause analysis on verification failures, identifying issues and recommending corrective actions.

Project Lead

Tech Mahindra Cerium Pvt. LTd.
01.2025 - 10.2025
  • Project name: Ethernect for KMS module
  • Client: Intel-Altera
  • Conducted regression tests and generated reports for Ethernet project, ensuring system reliability
  • Executed assertions to validate system functionality, enhancing software quality
  • Configured cron jobs for automated task scheduling, streamlining operational workflows

Functional Verification Engineer – Hardware Developer

IBM India Pvt. Ltd.
Bangalore
02.2024 - 12.2024
  • Project name: zVerification
  • Developed SSP DMA register monitor, ACE 4 lite responder driver, and related files, including tests for interrupts and FIFOs.
  • Established regression unit utilizing internal tools to streamline verification process.
  • The project was based on C/C++ language and used IBM internal verification tools Fusion, Mesa, HDWB and Nexa. Version control is done using GitHub. AXI/ACE and PCie are part of it. EWM was used for task/bug tracking.

ASIC Verification Engineer

Boeing India Engineering and Technology Center
Bangalore
02.2019 - 02.2024
  • Project name: Under NDA (RnD project)
  • Executed register model/bank testing from test planning through test sequence/case execution.
  • Designed passive UVC structures for mid-level re-assembly block and tailored I2C block.
  • Performed test regression runs and debugging of failures. Reported failures in JIRA.
  • Developed functional coverage construct.
  • Test/sequence coding for project-based design modules
  • Implemented bridge module for RGMII to SGMII data transmission.
  • The project was based on SV-UVM and used Cadence NCSim (Xcelium) for testing. It had Ethernet, PCIe, I2C etc. protocols as part of it. It used SVN for version control and JIRA for error logging.
  • Also worked on a NCSU training related project of creating a full test bench for a pipelined LC3 microcontroller using UVM-F.

Design Verification Engineer

Synapse Design
Bangalore
10.2017 - 01.2019
  • Project name: Gucci
  • Client: MegaChips and Extron joint project.
  • Executed end-to-end interface verification for HDMI Tx controller IP and main Blue-logic, ensuring functional integrity.
  • Developed RAL-based register configuration sequences for HDMI Tx controller IP functions, enhancing configuration accuracy.
  • Created tests for custom interrupt handler and system monitor register, validating system reliability and performance.
  • The project was based on SV-UVM and used Synopsys VCS for testing. It had HDMI, PCIe, I2C, SPI etc. protocols as part of it. It used SVN for version control and JIRA for error logging.

Design Verification Engineer

Aceic Design Technologies Pvt. Ltd.
Bangalore
03.2017 - 09.2017
  • Executed Bluetooth 5.0 VIP testing for back-to-back connections and developed BLE 5.0 Madrid Version VIP wrapper for in-house project.
  • Developed AMBA AHB 2.0 lite protocol single-master single-slave VIP during 1-month company training.
  • Designed and developed verification environment for arbiter (1 to 4 router) as part of training, leveraging SV-UVM with Aldec RivieraPro and QuestaSim.
  • The project was based on SV-UVM and used Aldec RivieraPro and QuestaSim for testing. Design was done on ISE Design Suite, Xilinx.
  • Company was acquired by Synapse, hence the short term of employment.

Education

ADVANCED VERIFICATION WITH UVM -

NCSU
Raleigh, North Carolina, USA
12-2022

VLSI-RN Certification Course -

Maven Silicon
Bangalore, Karnataka, India
03-2017

PG Certificate Course -

DKOP Labs Pvt. Ltd.
Noida, Uttar Pradesh, India
06-2016

Master of Technology - VLSI Design

GD Goenka University
Gurugram, Haryana, India
06-2016

Bachelor of Technology - Electronics And Communication Engineering

Amity University
Noida, Uttar Pradesh, India
06-2014

Certification Course - Embedded Systems using 8051 microcontroller and VHDL programming

CETPA InfoTech Pvt. Ltd.
Noida, Uttar Pradesh, India
07-2013

Skills

  • SystemVerilog
  • UVM skills
  • TestBench development
  • Constrained-Random testing
  • Testing skills
  • EDA Tools
  • Shell scripting
  • Version control
  • Agile project management
  • Microsoft Office
  • Time Management Skills
  • Interpersonal Skills
  • Teamwork
  • Communication Skills
  • UVM skills

Languages

Bengali
Advanced (C1)
C1
Hindi
Beginner
A1
French
Beginner
A1
English
Advanced (C1)
C1

Timeline

Senior Technical Lead

Quest Bitsilica Services Private Limited
06.2026 - Current

Senior Staff Design Verification Engineer

Insemi-Infosys
10.2025 - 05.2026

Project Lead

Tech Mahindra Cerium Pvt. LTd.
01.2025 - 10.2025

Functional Verification Engineer – Hardware Developer

IBM India Pvt. Ltd.
02.2024 - 12.2024

ASIC Verification Engineer

Boeing India Engineering and Technology Center
02.2019 - 02.2024

Design Verification Engineer

Synapse Design
10.2017 - 01.2019

Design Verification Engineer

Aceic Design Technologies Pvt. Ltd.
03.2017 - 09.2017

ADVANCED VERIFICATION WITH UVM -

NCSU

VLSI-RN Certification Course -

Maven Silicon

PG Certificate Course -

DKOP Labs Pvt. Ltd.

Master of Technology - VLSI Design

GD Goenka University

Bachelor of Technology - Electronics And Communication Engineering

Amity University

Certification Course - Embedded Systems using 8051 microcontroller and VHDL programming

CETPA InfoTech Pvt. Ltd.

Hobbies and Interests

  • Reading
  • Cooking
  • Art and Craft
  • Singing
  • Anime/Manga

Personal Information

  • Date of Birth: 06/16/91
  • Nationality: Indian

Similar Profiles

CREATE PROFILE
Sanjana Mookim