Jayesh Gidwani

Aspiring Electronics Engineer with hands-on experience in Custom IC Layout, Analog & Mixed Signal Circuit Design, and Cadence EDA tools. Skilled in schematic-to-layout flow, DRC/LVS verification, parasitic extraction, and circuit optimization. Strong foundation in circuit theory, device electronics, and automation scripting (Python, TCL, SKILL). Passionate about VLSI and Analog Design.

• Design, Implementation and Characterization of Charge Pump for High-Speed PLL | Major Project (2025)
  - Designed a charge pump for high-speed PLL with emphasis on low jitter and low power.
  - Created layout in Cadence Virtuoso, verified with DRC/LVS using Assura, and analyzed parasitic impact.
  - Currently Working
• RTL Design of 4-bit ALU | Academic Project
  - Developed a 4-bit Arithmetic Logic Unit in Verilog with ADD, SUB, AND, OR, XOR.
  - Verified functionality using testbenches and simulated in ModelSim.
• SoC Bus Protocol Simulation (AXI4) | Course Project
  - Simulated Advanced eXtensible Interface (AXI4) transactions using SystemVerilog.
  - Implemented handshaking, burst transfer, and arbitration logic with coverage metrics.
• CNN Accelerator on RISC-V | Research Project
  - Engineered a CNN hardware accelerator achieving 3x faster inference with 60% power savings.
  - Integrated with RISC-V SoC and validated through FPGA prototyping.

• English
• Hindi
• Kannada

• Cube solving
• Playing badminton
• Exploring nature