N Akshay Urs

Organized individual with a strong background in hardware testing and system integration under tight deadlines. Having worked and led the electrical division for an FSAE racing team, I’ve developed a practical approach to troubleshooting and coordinating complex vehicle electronics. I am eager to take on new challenges across the electronics field, from design to testing, while helping the team reach its goals.

Design and VLSI implementation of a Fair Weighted Round-Robin Bus Arbiter for Multi-Core RISC-V Network-on-Chip (NoC)

Dec 2025 – Present

Engineered a 100 MHz bus arbitration unit for multi-core RISC-V architectures using SystemVerilog. Validated performance via Cadence Genus synthesis, achieving a 50% timing margin (5.05 ns slack) on a tsmc18 process.

Crop Type and Health Detection Using Hyperspectral Imaging and Machine Learning

Apr 2025 – Jul 2025

Utilized publicly available hyperspectral datasets to classify crop types and assess crop health using machine learning models. Applied techniques like PCA for dimensionality reduction and trained classifiers such as SVMs on python.

Ultrasound-Based Wireless Communication System as an Alternative to Optical Fibers

Feb 2025 – Apr 2025

Developed an analog circuit-based system using op-amps and ultrasonic transceivers to establish wireless communication between two computers over a distance of 30 cm.

Thermal Management System for CPUs and GPUs Using Peltier Modules

Feb 2024 - June 2024

Designed and implemented a thermal management solution using Peltier modules to actively cool CPU temperatures, reducing heat from ~80°C to ~42°C.